SU1635288A1 - Receiver of tone signals - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to improve the noise immunity. The receiver contains a matching unit 1, a pulse former 2, a frequency divider 3, an inverter 4, one-oscillators 5, 6 and 18, elements OR 7 and 16, delay elements 8 and 9, a counter 10, a clock generator 11, a coincidence unit 12, a decoder 13, the O-flip-flop 14, the drive 15 and the execution unit 17. The drive 15 provides temporary protection of the receiver against false alarms, for example, if there is a voice signal at the input. The goal is achieved by ensuring the formation of a reset signal for the accumulator 15. 2 Il.

Description

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The invention relates to communication technology, in particular to digital signal processing, and can be used in measurement technology, telephone communication technology, etc. for receiving single-frequency sinusoidal signals.

The purpose of the invention is to improve the noise immunity,

Figure 1 shows the structural electrical circuitry of the tone receiver; 2 shows timing diagrams for his work.

The tone receiver contains a matching unit 1, a pulse shaper 2, a frequency divider 3, an inverter 4, a first 5 and a second 6 one-oscillators, a first element OR 7, a first 8 and a second 9 delay elements, a counter 10, a clock generator 11, a block 12 matching, the decoder 13, D-trigger 14, the drive 15, the second element OR 16, the Executive unit 17, the third one-shot 18.

Receiver tones works as follows.

The input signal (Uo figa) through the matching unit 1, which provides high input impedance, is converted into a pulse sequence (U2 fig.2b) by the shaper 2, which can be used as a threshold device (or comparator), eliminating the possibility of false alarms with weak input signals (noise). The spread of the positive and negative half-wave durations of the 1) 2 signal is eliminated by a divider of 3 frequencies by 2, the output signal of which is shown in Fig. 2c. With the help of an inverter 4, one-shot 5, 18, and the element OR 7, short pulses are generated, which switch the output of the counter 10 through the block 12 to match the decoder 13 and, with a small delay, embed the counter 10. The output signals of the element OR 7 (U) and element 8 delays (Ua) are shown in fig.2g and d, respectively. The counter 10, which counts the pulses of the high-frequency signal supplied from the first output of the clock generator 11, measures the duration of each period of the input signal, since the counter 10, unlike the prototype, occurs during both the positive and negative half-periods of the output signal of the divider 3 frequencies. The decoder 13 periodically checks whether the duration of each period is within the specified limits, and generates at its output the pulses fed to the drive 15.

If a, b, c are binary numbers at the output of counter 10 (at the time of reading to the decoder 13 through the block 12 matches), the lower and upper values of the permissible values of the durations of periods, then the pulse at the output of the decoder 13 is only

with simultaneous fulfillment of conditions a b and a c, which is verified by comparing the indicated binary numbers.

The drive 15 provides temporary protection of the receiver against false alarms, for example, if there is a speech signal in the input signal. The drive 15 may be made, for example, on the basis of an asynchronous binary counter connected to an additional decoder that determines whether the number accumulated by the counter is less than or greater than the specified one. In the latter case, the executive unit 17 is given a signal causing it to trigger. A periodic reset signal is sent to the Nekopitel 15 from the output of the clock generator 11 through the OR 16 element, which can be formed by dividing a high frequency (supplied to the counter 10) and then feeding the divided frequency to the one-shot 6 to form short pulses along the front or rear fronts divided frequency. It is also possible to build drive 15 on the base

0 serially connected integrator with reset and threshold device. If the durations of all periods of the input signal are within the specified limits, the pulses from the output of the decoder 13 (signal Ui3.

5 of FIG. 2g) are periodically fed to accumulator 15. If the duration of a period, for example, in the interval (Fig. 2b) is outside the specified limits, the pulse at the output of the decoder 13 does not appear. In addition, an extraordinary reset signal Uie is generated (Fig. 2h). supplied to the accumulator 15. The reset signal Uie is formed as follows. By the time of the occurrence of the transition edge of the signal Ue (at the output of the delay element 8), the output signal of the decoder 13 is zero (the period of FIG. 2a lies outside the specified limits), the inverse output D-flip-flop

0 14 a unit appears, which, by triggering the leading edge of the second one-shot 6, generates at the output of the last a signal U IB resetting the accumulator 15, which provides an additional increase in the noise immunity of the device.

Using the first delay element 8 per hectare (Fig. 2e), the signal Ue is formed by the leading edge of which the output signal of the decoder 13 is recorded in the D-flip-flop 14 Slightly before the moment of occurrence

the signal at the output of element 8 to the input of block 12 coincidence from the element OR 7 receives a signal 117 (Fig. 2d), which connects the output code of counter 10 to the input of the decoder 13. A delay of the strobe signal Us is necessary to complete the transients in block 12 of coincidence and decoder 13 After the process of writing information to the D-trigger 14 is completed, a reset signal Ug (Fig. 2e) is returned to the counter 10 from the output of the second delay element 9, which returns the counter 10 to the initial (zero) state.

The matching unit 1 can be designed as an amplifier with a large input impedance.

Claims (1)

The invention includes a tone receiver comprising a series-connected matching unit, a pulse shaper and a frequency divider, a series-connected decoder, a drive and an execution unit, a counter, a clock generator and a matching unit, characterized in that In order to improve the noise immunity, the first one-shot, the first OR element, the first delay element and the second the delay element, the output of which is connected to the input of the installation O of the counter, the outputs of which are connected to the first inputs of the coincidence unit, the outputs of which are connected to the inputs of the decoder, the output of which is connected to the information input of the D-flip-flop, the inverse output of which is connected to the first input of the second element OR, the second input of which is connected to the first output of the clock generator, the second the output of which is connected to the clock input of the counter, the output of the second element OR is connected via the second one-shot to the second input of the accumulator, the output of the frequency divider is connected to the inputs of the first one-shot and an inverter, the output of which is connected to the second input of the first OR element through the third one-shot; the output of which is also connected to the second input of the coincidence unit.