SU1635180A1 - Device for square root computing - Google Patents

Abstract

The invention relates to computing and can be used in digital automation systems. The aim of the invention is to improve the speed of the device while simplifying. For this purpose, a unitary code generator, a group of AND elements and a group of OR elements are entered into a device containing an adder, two registers, a control unit. The group of elements OR performs the function of addition, since in the algorithm under consideration nonzero bits of the unitary code correspond to zero bits of the contents of the second register. A group of elements And perform the masking of non-zero bits of the unitary code at a low level at the corresponding output of the control device. 2 Il. a Ј /

Description

The invention relates to computing and can be used in digital automation systems to speed up the operations of integer arithmetic.

The purpose of the invention is to increase speed while simplifying the device.

FIG. 1 shows a block diagram of the device; on rig. 2 - an example of the implementation of the generator unitary code.

The circuit contains adder 1, first 2 and second 3 registers, generator 4 of unitary code, group of elements AND 5, group of elements OR 6, control unit 7 containing trigger 8, elements AND 9 and OR 10, triggers 11 (FIG. 2) and elements 12, output 13 and input 14. The device implements the calculation algorithm:

0 OO

cl

00

 141

 and

BUT; + e; (Р; + ч; - Р; / 2 + El q;

chi, 8

q; /;,., sign A;

where a is the contents of register 2; P - the contents of register 3; q is the weight of a unitary unit;

Ј- the sign of the number at the output of the adder

With A - (N + 1), pb-0, qfl 2gt) (where m 2t 0.5 log N is an integer) at iteration number m we have: Pm т m 0.

The device works as follows.

In the initial state at a high level, the sync input from the output of the first register 2 pa input of the adder will receive the inverse code of the number N, i.e. the number - (N + 1), to the input of the group of elements AND 5 from the output of the generator 1, the output 1t is the number 22t, where ha is 0.5 log, (the contents of the second register 3 is zero),

Each iteration consists of two phh: phases of the stripping (high: the level of the sync signal) and the phase of the recording (the low level of the sync signal). During the comparison phases, the contents of the PG 1 register (iteration variable A) are compared with the logical sum of the contents of the o-th PG2 (iteration variable P) and the generator code (iteration variable q). If the output of the adder bit is low y1 odn (iterative variable Ј pav nl 0), then in the recording phase, the number from the OUTPUT of the generator is added to the reduced content of PG2, and the contents of the register PG1 becomes equal to compare. If the iterative process is characterized by a sequence of vectors with components, p, q, Јj, then the sequence of such vectors when calculating the square root of 225 has the form:

-226 0 64 1

-126 64 16 1

-82 48 4 1

-30 28 1 1

-1 15 O 1, where the result is the second component of the last vector, and the ending sign is the zero value of the third component.

The advantage of the proposed device is that, first, a relatively small (about 62) number of transistors is required in terms of discharge when implementing the device according to integrated CCOM technology, which, combined with the simplicity of interconnecting connections, makes it possible to crystals of a small area

,

Q 5

up to 50

D5

P

five

0

five

spade Reducing the area of the crystal increases the number of suitable chips obtained by integrated technology from a single plate, and, accordingly, reduces the cost of one chip.

Secondly, a single adder and a small extension of the signal distribution circuits, both in terms of the number of logical elements and in the absolute value of the communication lines, makes it possible to significantly reduce the conversion period, especially since the propagation time of transfer in the adder is significant only at the last iterations, when the weight of the unit is low and the reading code is small enough

Claims (1)

Formula invention A device for calculating the square root containing the adder, the first and second registers, the output and the information input of the first junction of which are erased; are given, respectively, with the first in p - p; o and the output of the adder, characterized in that with a PODPZG- circuit. speed with simultaneous operation of the device, the dc is introduced. The unitary code slot, the group of elements is AND, the group of elements OR, and the control unit, whose information input is connected to the output of the sign bit, the adder, and the first output to the control input of the first register, whose additional information input is the information input of the device, the synchronization input cots; It is connected to the control inputs of the generator unitary code, control unit and second register, the outputs of which are connected to the first inputs of the OR elements, the second inputs of the OR elements of which are connected to the outputs of the corresponding AND elements of the group, the first inputs of the AND elements of which connected to the generator outputs of the unitary code, and the combined second inputs are connected to the second output of the control unit, the outputs of the OR elements of the group are bitwise connected to the second input of the adder and shifted by one bit to the right - With the information input of the second register, the high order bits of the OR elements of the group are the output of the device. UCL 5Ј Cnform 6x. j a That i C1 V w and t Ishrorm SYJIffx D 15 Exit 1 / eight // Y / / / z rz - .J