SU1633411A2 - Device for testing and diagnozing faults in logic units - Google Patents

Description

1 (61) 1441405

(21) 4663954/24

(22) 03/20/89

(46) 03/07/91. Bul Number 9

(72) V.S. Pivovarov and V.N.

(53) 681.3 (088.8)

(56) USSR Copyright Certificate No. 1441405, cl. G 06 F 11/16, 1986.

(54). DEVICE FOR INSPECTION AND DIAGNOSTICS OF FAILURES OF LOGICAL BLOCKS

(57) The invention relates to computing, can be used to monitor and diagnose typical replacement elements for electronic computers, and is an improvement on the known device described in the author's certificate No. 1441405. The purpose of the invention is to expand the scope of application of the device by providing monitoring and diagnostics blocks, including programmable nodes or circuits, functioning with the ordered change of signals on separate groups of input contacts. The device contains two electrical matching units, a display unit, a comparison unit, a synchronization unit, a pseudo-random sequence generator, a switchboard, a toggle register, a control unit, a fault recording unit, a register, an address counter, an ultra-fast memory unit. 1 il.

The invention relates to computing, can be used to monitor and diagnose typical replacement elements for electronic computers, and is an improvement to the device according to the author. St. No. 1441405.

The purpose of the invention is to expand the field of application of the device by providing monitoring and diagnostics of blocks, including programmable nodes or circuits that operate when ordered signals change on separate groups of input contacts.

The drawing shows a block diagram of the device.

The device for monitoring and diagnosing malfunctions of logic blocks contains a pseudorandom sequence generator 1, register 2, a toggle register 3, switch 4, two blocks o and 6 electrical matching, a reference block 7, a monitored block 8, a fault recording block 9, a display 10 block, a block 1 1 synchronization, counter 12, control block 13, comparison block 14, address counter 15, slug memory block 16.

The non-volatile memory unit 16 serves to store and output information via switch 4 to the monitored units. An over-speed memory can be performed on integrated circuits with a read cycle shorter than the duration of the device operation cycle.

The device works as follows.

The pseudo-random sequence generator 1 provides for issuing the check code of dynamic pseudo-random sequences to the switch inputs. The number of generator outputs is determined by the maximum number of contacts of the tested blocks. Using the toggle register 3 and switch 4, the input contacts of the logic blocks are selected and the input signals are switched.

The input signals to the monitored block 8 and the reference block 7 are fed through blocks 5 and 6 of electrical matching and can be fed to different contacts from a pseudo-random sequence generator 1 from block 1 I synchronization, block 13 of control, block 16 of a fast memory in various combinations

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In the operation of the device there are two.

In the control mode, the initially monitored and reference blocks are brought to the identical state. Then the working period of the control begins. The moment the blocks are brought to the identical state is automatically detected, and in block 13 the signal "Start of comparison is generated. In the control mode, the state of the pseudo-random code generator periodically stored in register 2 to enable cyclic repetition of sequences of input signals at which

a malfunction occurs. Then the blocks of the device are reset to the initial state. The cycle repeats automatically from the start of the pseudo-random code generator from the initial state.

5 In the second cyclic mode, when searching for a fault, a sequence of input signals is jammed, in which the source information for generator 1 is register 2 information. The second cyclic mode is used in troubleshooting in blocks that do not lead to the same state due to gross faults

Using information about an malfunction. At that, the information from the dictation of error triggers is read cyclically through all the addresses using the oscillation memory and fed to the selected group of input contacts of the monitored and the reference blocks. errors of the fault registration block 9 and in block 13 a signal is generated "Stop, by which the operation of the device is blocked, by block 10 is indicated Omer incomparable shihsy contacts For troubleshooting, a first and second cyclic modes

During the first cyclic mode, the control unit blocks the generation of the Stop and Reception signal to register 2, where the state of generator 1, which precedes the information that caused the fault, is stored. After restarting the device, the information on generator 1 changes from the initial state. blocks to an identical state. Generator 1 receives information from register 2 and the monitoring period begins. The moment is fixed.

25

the principle of failure

Claims (1)

20 Formula of Invention A device for monitoring and diagnosing malfunctions of logic blocks according to avto No. 1441405, characterized in that, in order to expand the field of application of the device by providing monitoring and diagnostics of logic blocks, including programmable nodes or circuits that operate when individual ipynnax input contacts, a super-fast memory block and an address counter are entered into it, the input of the initial installation of the address counter is connected to the fifth output of the control unit, the counter input of the counter the address is connected to the first output of the control unit- 2g; the output of the address counter is connected to the address inputs of the super-operative memory block, the output of which is connected to the fifth group of information inputs of the commutator thirty a malfunction occurs. Then the blocks of the device are reset to the initial state. The cycle repeats automatically from the start of the pseudo-random code generator from the initial state. In the second cyclic mode, when troubleshooting, a sequence of input signals is jammed, in which the source information for generator 1 is register 2 information. The second cyclic mode is used in troubleshooting in blocks that do not lead to the same state due to gross faults When using information about in .dication of error triggers using oscillation25 the principle of failure 20 Formula of Invention A device for monitoring and diagnosing malfunctions of logic blocks according to avto No. 1441405, characterized in that, in order to expand the field of application of the device by providing monitoring and diagnostics of logic blocks, including programmable nodes or circuits that operate when individual ipynnax input contacts, a super-fast memory block and an address counter are entered into it, the input of the initial installation of the address counter is connected to the fifth output of the control unit, the counter input of the counter the address is connected to the first output of the control unit- 2g; the output of the address counter is connected to the address inputs of the super-operative memory block, the output of which is connected to the fifth group of information inputs of the commutator thirty