SU1626344A1 - Pulse generator - Google Patents

Abstract

The invention can be used in software-controlled systems for generating pulses with the possibility of varying the duration of both a pulse and a pause over a wide range and for forming a pulse sequence. (Spruce of the invention is the extension of functionality due to independent regulation of the pulse-post-pulse and pause. The pulse generator contains the master oscillator 1, the elements 2, 10 and 11, the triggers 4 and 12, the frequency divider 5, the counter 13 pulses, the sensor 18 duration pulse and pulse number sensor 19. To achieve this goal, an And 3 element, multiplexers 6 and 7 are introduced into the pulse generator, dividers 8 and 9 with a variable division factor, inverter 14, pause and pulse clock sensor 15 and 16, and duration sensor 17 1 auzy yl

Description

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The invention relates to k pulse technique and can be used in software systems for generating pulses and pulse sequences.

The aim of the invention is to enhance the functionality of the pulse generator by independently adjusting the pulse duration and pause.

The drawing shows the functional diagram of the pulse generator.

The pulse generator contains the master oscillator 1, the first element And 2, the three-input element And 3, the first trigger 4, the frequency divider 5 (decade), the first multiplexer 6, the second multiplexer 7. the first frequency divider with variable division factor (DPKD) 8, the second frequency divider with variable division factor (DDCD) 9, the second element And 10, the third element And 11, the second trans 12, the counter 13 pulses (subtracting), the inverter 14, the sensor 15 clocking pause, sensor 16 clocking pulse, sensor 17 the duration of the pause, the sensor 18 pulse duration a sensor 19 and the number of pulses

The output of the master oscillator I is connected to the first input of the first element I 2, the output of which is connected to the counting input of divider 5, the output of which is connected to the information inputs of multiplexers 6, 7, the control inputs of multiplexer 6 are connected to the outputs of pause clock 15, control The inputs of the multiplexer 7 are connected to the outputs of the pulse timing sensor 16, the output of the multiplexer 6 is connected to the counting input of the PDKD 8, whose information inputs are connected to the outputs of the sensor 17 for the duration of a pause, and the output is connected to the second The input element of an AND 10, the output of which is connected to the setup input of the DCDD 8 and the first input of the trigger 12, whose direct output is the generator output, and the inverse output is connected via an inverter 14 to the enable input of the multiplexer 6, the output multiplexer 7 is connected to the counting input of the DPKD 9, whose information inputs are connected to the outputs of the pulse duration sensor 18, the output of the DPKD 9 is connected to the counting input of the counter 13 and the first input of the I 11 element whose output is connected adjusting input DPKD 9 and the second input of the flip-flop 12, a second input of AND gate 11 connected to the output of AND 3 VTOO input of flip-flop 4 and the adjusting input

the counter 13, the information inputs of which are connected to the outputs of the sensor 19 of the number of pulses, and the output of the counter 13 is connected to the first input of the three-input element And 3, the second input of which is connected to the generator mode selection bus, the third input of the three-input element And 3 is connected to the generator installation bus, the second the input element And 10 and the first input of the first trigger 4 are connected to the trigger bus, the direct output of the first trigger 4 is connected to the second input of the first element 2.

The pulse generator works as follows.

The information inputs of the pulse generator are the information inputs of the 1G-19 sensors. Before starting work, the corresponding code must be installed on the information inputs of the sensors. The control inputs of the generator are mode select buses (second input of AND 3 element), installation bus (third input of AND 3 element). launch bus (first trigger input 4 and element input 10). Before starting work, all control inputs must have a single level from the button or programmatically.

A low level pulse is applied to the generator setup input, which from the output of element I 3 arrives at the second input of trigger 4 and sets a low level at its direct output that prohibits the passage of the clock frequency from the master oscillator I through element 2. At the same time, the low level signal from output element And 3 enters the installation vggd subtractive counter 13. skid into it the code of the number of pulses from the output of the sensor 19, as well as through the second input element And 11 enters as the setup input DPKD 9 skid into it od pulse width output from the sensor 18 and sets the output to the forward trigger 12 (vylod generator) low level and the high level inverted output from flip-flop 12 disables the operation of multiplexer 7 and through an inverter 14 enables the multiplexer 6.

A low level pulse is applied to the trigger input of the generator. This pulse, through the second element 10, sets the pause code from the output of the sensor 17 into the DPCD 8 and generates the forward front of the output pulse of the generator at the forward output of the trigger 12, and a low level is formed at the output of the trigger 12 enabling the operation of the multiplexer 7 and through the inverter 14 prohibiting multiplexer operation 6. Simultaneously, the triggering pulse sets trigger 4 to one state and allows the clock frequency to pass from master oscillator 1 to the counting input of the ten-day frequency divider 5, at the output of Secondly, n frequencies of multiples of ten are formed (n is the number of the decade-decade frequency divider 5), which arrive at the information inputs of multiplexers 6 and 7, at the control inputs of which pause and pulse clock frequency codes are set, respectively. The corresponding frequency selected by the multiplexer is fed to the counting input of the DCD 9, the information inputs of which have the pulse duration code set, i.e. the code that determines the retention time at the output of the trigger 12 of the unit level. At the end of the counting at the output of DCDD 9, a low level pulse is generated, which arrives at the counting output of the subtractive counter 13-, decreasing its value by one, and through the first input of the And 11 element to the setup input of DCDD H and also to the second input of the trigger 12 This pulse enters the pulse duration code in the DPKD 9, preparing the DPKD 9 for further operation, and at the same time at the forward output of the trigger 12, the rear pgnt of the external pulse of the generator a MI is detected. t e is set to the level that disables the r-w / u m and plexor 7 (thus chtsh.sh t to t t, t DPKD 9 ceases delivery ruyuschih whether tat-pulses) and chergch inverter 1 1 allows operation of the multiplexer g)

The selected multiplier keyori 6 substitute frequency is fed to the IH counting input of the DCPD 8 into which we enter the pause code and the code defining the pprrm of the output at the low-level terriorp output. At the end of the HI Hm o, / DKD88 counting, the imp / l1G np and gp / | from n, which: nd arrives at the gloves under the element and output output of the ULTS G-LRG RNTs

And 10 prepares the PDKD 8 to form the next pause and translates trigger 12 into a single state to form the leading edge of the next pulse simultaneously from the inverse trigger / trigger) 12 low: the level inhibits the operation of multiplexer 6 and enables the operation of the multiplexer 7. Thus, the formation of the next impulse output begins the generator frequency, generator oscillator frequency is repeated, with each one of the frequency pulse of the DPCD 9 output decreasing the value of the subtracting counter 13 by one. When the number of pulses received at the counting input of the subtracting counter 13 reaches the set number of pulses, the internal bits of the subtractive counter 13 are zeroed and a low level pulse is generated at its output, which through the first input

element And 3 enters as the installation input of the subtractive counter 13, the skid

new pulse number code value

on the second input element And 11, skidding in

DPKD 9 new value code duration

pulse, sets the forward output of the trigger 12 to a low level, and sets the forward output of the trigger 4 to a low level, which prevents the clock from passing the master oscillator 1 to the counting input of the ten-day frequency divider 5, thus completing the formation of a sequence with a specified number pulses

impulses it is necessary to re-apply the impulse to the generator.

If it is necessary to form an unlimited sequence of pulses, a low level i signal is sent to the control input of the generator mode selection and the tripler 1 will not be switched when the output pulse is received from the subtracted counter 13 of the input clock frequency

the counting decadal divider of 5 frequencies and preriptation will not be but the formation of pulses and a pause will be, anapically described change occurs. Change of the memeor, t | We are typing 11 g with an iterator of the signals of the pro

i o, un g set by the corresponding chutz11 and for i i ch1- and 15 1e)

Offer a toner op e hmp / e .o provides, as well as possible, to control both the impulse frequency pulse and the nav pulse.

3ii rtchchechchot metot t ppppe izgno I1 dota / plus 11 i ii- urinyiuc.j tl and riavi: s as well as fprch-roor n1 1 impug go- as in continuous mode and in the mode with zp / iaiiHUM number of pulses at

sequences

Claims (1)

The invention The impulse generator soder-chashas / L is a master oscillator of a pulse counter, frequency divider, counters and second triggers, an impulse count sensor, an impulse length sensor, the first, second and third elements And, the first input of the second element And connected to the first pass per of the first trigger and to the startup bus, from which it is so that, in order to expand the functionality, it additionally introduces the first and second multiplexers, the first and second frequency dividers with a variable division factor, an inverter, a three-input element A, pause and pulse clocking sensors, pause duration sensor, the counting input of the frequency divider is connected to the output of the first element I, and the outputs are connected to the information inputs of the first and multiplexer support, the control inputs of the first multiplexer Adjacent to the outputs of the pause clocking sensor, the control inputs of the second multiplexer are connected to the outputs of the pulse clocking sensor, the output of the first multiplexer is connected to the counting input of the first divider with variable division factor, the information inputs of the coagulation sensor are connected to the outputs of the pause duration, and the output is connected to the second input of the second element And, the output of which is connected to the installation input of the first frequency divider with alternating division ratio and the first input of the second trigger, directly whose output is the output of the generator, a second rigger inverse output is connected through an inverter to the enabling input of the first multiplexer and directly oazre- shayushim input of the second multiplexer the output of the second multiplexer is connected to the counting input of the second frequency depot with a variable division factor, the information inputs of which are connected to the outputs of the pulse duration sensor, the output of the second frequency divider with a variable division ratio is connected to the counting input of the pulse counter and to the first input of the third And element whose output is connected with the installation of the second frequency divider with a variable division factor and the second input of the second trigger, the second input of the third element And is connected to the output three-input element And, the second input of the first trigger and the stable input of the pulse counter, the information inputs of which are connected to the outputs of the number sensor (impulses output the pulse counters connected to the first code of the three-output element And moooi1 dod i heating is connected to the mode selection bus a the third output is connected to the generator installation bus, the direct output of the first trigger with osdeppep with the second input of the first element I, the first input of which is connected to the output of the generator giving generator