SU1624700A1 - Decoder - Google Patents

Abstract

The invention relates to telecommunications and can be used in digital information transmission systems. The decoder performs majority-logical decoding using the information symbols of the adjacent channels as an additional check character code, which increases the decoding confidence. The decoder contains a shift register, digital processing channels with blocks of adders modulo two and a majority element, each read block on elements I. The coder contains a shift register and modulator two. 2 Il.

Description

The invention relates to telecommunications and can be used in digital information transmission systems.

The purpose of the invention is to increase the reliability of the decoder.

Figure 1 presents the functional diagram of the decoder; 2 shows the friction scheme of the coder.

The decoder contains (1) shift register 1, digital processing channels 2, each of which is performed on block 3 modulo-two adders and majority element 4, read block 5 performed on AND elements 6 and outputs 7-37 of shift register 1.

The encoder contains (figure 2) the register 38 shift, the adder 39 modulo two and information inputs 40 of the register 38.

For example, consider the decoder (figure 1), containing n 5 channels 2 digital processing. In this case, register 1 contains 2 - 1 31 cells, the outputs of which are connected to modulators two blocks 3 of the 1st channel 2, i 1, 5, according to the expressions

ai aiai + en-e | AI-7 + an22

ai a and + an-18 a, an-6 + an-27 ai ai + tz + a 1 + 14 ai ai + 2 + ai + s ai ai + 3 + ai + 29 ai an-26 + ai + 28 ai an-4 + an-ai a-an-12 + ai + 23 ai ai + 2i + ai + 23 ai an-8 + ai + 20 ai ai-is + an-24 at ai-m + ai-see

WITH

R

l xi

where ai-hj is the output of (l + j) -u register cells 1, with the indices being modulo 2n-1 31.

The decoder decodes the M-sequence code formed on the basis of the polynomial f (x) x5 + x2 + 1 and formed by the encoder (Fig. 2).

The device works as follows

Binary channel symbols arriving at the information inputs 40 of the encoder (FIG. 2) with a cyclic control signal

the synchronization is recorded in the cells of the registry 38. At the end of the recording pulse, the registry 38 is shifted to the shift mode and under the action of the clock pulses using the adder 39 modulo two generates a linear recurrent sequence with initial conditions corresponding to the values of the binary channel symbols.

The M-sequence formed by the encoder is fed to the information input of the decoder (Fig. 1) and, under the influence of clock pulses, is written to the shift register 1 and fed to the inputs of channels 2. In each channel 2 binary symbols are formed, representing the result of adding modulo two contents register cells 1, and at the moment the cyclic sync pulse arrives at the outputs of block 3 adders, in each channel 2 I forms 15 channel signal variants. All I variants of the information signal are sent to the majority element 4, which The second assigns the output binary symbol a value determined by the majority principle.

The cyclic sync pulses also arrive at the control input of the readout unit 5, the information inputs of which from the outputs of the majority elements 4 receive channel signals. At the outputs of read block 5, the values of the output channel symbols are generated at the moments of arrival of cyclic sync pulses.

Compared to the prototype, the proposed decoder can improve the reliability of decoding binary information by applying a correction code with redundancy in the form of a linear recurrent sequence with a majority-logical decoding of the latter. If in the prototype the probability of an erroneous estimate of the transmitted binary symbol is Pt, then in the proposed decoder this probability decreases and is equal to

I

P2 2 C

g 1/2 + 1

Pl (l-pl)

In the proposed decoder, in forming the information symbols of each channel 2, in addition to the verification code symbols, the information symbols of the adjacent channels are also used. The efficiency of majority-logical decoding depends on the number of I checks organized in block 3 of each channel 2. Thus, with I 15 and the evaluation of the binary symbol

with an error probability of PI 0.1, the probability of erroneous decoding of a binary symbol at the output of any channel 2 is P2 0.0013. The invention allows for varying decoder characteristics, since

Reducing the requirements for the value of Pa leads to a reduction in the number of checks I and, as a consequence, to a reduction in the code length.

Claims (1)

Invention Formula A decoder comprising a register and a main channel of digital processing performed on a block of adders modulo two and a majority element, the outputs of a block of adders modulo two are connected to the corresponding inputs of the majority element, the outputs of the register are connected to the corresponding inputs of a block of adders modulo two main channels of digital processing, characterized in that with In order to improve the reliability of the decoder, a read block and additional digital processing channels are introduced in it, each of which is made similarly to the main digital processing channel, the inputs of the modulo adders blocks two additional digital processing channels are connected to the corresponding register outputs, the outputs of the majority elements of the main and additional digital channels The processing is connected to the corresponding information inputs of the readout unit, the information input and the register clock input are respectively the information input and the input the clock synchronization of the decoder, the control input of the register is combined with the control input of the readout unit and is the input clock of the decoder, the outputs of the readout unit are 0 decoder outputs, FIG. one Yu, 402 f f y sh FIG. 2  i about J5 -