SU1622953A1 - Device for receiving discrete frequency signals - Google Patents

Abstract

The invention relates to radio and can be used in radio information transmission systems for receiving discrete frequency signals. The purpose of the invention is to simplify the device by eliminating several processing channels. The device receiving discrete frequency signals contains a band-pass filter 1, a mixer 2, a dispersion delay line 4, a linear frequency-modulated generator 3, an envelope detector 5, a key 6, a threshold generation unit 7, comparator 11, distributor 12 pulses, blocks 13 counters, multi-digit register 14, digital matched filter 15, threshold block 16, registering block 17 and synchronizer 18 "The device is based on frequency-time mennom radio preobratovangi via dispersive delay line 4, the mixer 2 and the generator 3 with linear frequency modulation, time selection RF pulse and the subsequent demodulation of the discrete frequency signal 4 yl. and S (L about yuo with | sd with

Description

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The invention relates to radio communications and can be used in radio information transmission systems for receiving and demodulating discrete frequency signals (DFS).

The aim of the invention is to simplify the device by eliminating several processing channels.

Fig. 1 shows a structural electrical circuit of the device; FIGS. 2-4 are time-frequency diagrams explaining its operation.

The device contains a band-pass filter 1, a mixer 2, a linear frequency modulated (chirp) generator 3, a dispersion delay line 4 (DLZ), an envelope detector 5, a key 6, a threshold generation unit 7 consisting of first 8 and second switches and threshold calculation units 10, comparator 11, pulse distributor 12, counters block 13, multi-digit register 14, digital matched filter 15, threshold block 16, recording unit t7, synchronizer 18 consisting of master oscillator 19, clock generator 20, first 21 and second 22 binary counters, decoder 23 and counter 24.

The device receiving discrete frequency signals is as follows ,,

At the input of the bandpass filter 1, a radio signal is received, which is the sum of interference and DFS transmitted by a sequence of radio pulses of duration T (Fig. 2a). The carrier frequencies of DPS radio pulses f j, left can have arbitrary (not equal), but known spacing intervals. The number of carrier frequencies is N, C of the output of filter 1, which limits the interference spectrum and has a bandwidth slightly higher than the frequency band occupied by DFS, the radio signal is fed to the first input of mixer 2. The second input of the mixer 2 is oscillated from the chirch generator 3, triggered by short pulses from synchronizer 18 at time intervals with “T (FIG. 26). The frequency deviation of the chirped oscillator 3 is approximately equal to the bandwidth passed by the bandpass filter 1, and the instantaneous frequency varies from its minimum to maximum value during time C, C (Fig. 2c, Over).

With the help of oscillations of the chirp generator 3, the sum of the interference and radio frequency pulses of the DFS is converted by the mixer 2 into continuous sequences of elementary chirped radio pulses of intermediate frequency. For example, when interference with the frequency fn in the passband of the filter fn is used, the time-frequency graph of the elementary chirped radio pulses at the output of mixer 2 has the form shown in FIG.

The signal from the mixer output is fed to the DL4 input. 4. For time-frequency conversion and guaranteed detection of the input radio pulses, the DLZ is a matched filter for the elementary chirp radio pulses. Different frequency components of one elementary LFM radio pulse propagate in a SLD with different speeds due to its dispersive properties and add coherently. As a result, a time-compressed (shortened in duration) compression ratio K times radio pulses are formed at the output of the SLR (FIG. 36). The amplitude of these radio pulses is proportional to the level of the frequency components of the noise and radio frequency pulses of the DFS, and therefore contains information on the power of the interference and radio pulses of the DFS, as DLZ 4 is a linear matched filter. is determined by the arrival of the corresponding frequency components coming from the output of the band filter 1 "

Detector 5 removes the internal modulation and extracts the envelope of the compressed radio pulses (Fig, S2d). The signal from the output of the envelope detector arrives at the first input of the 6 key. At its second input, during each time interval / t, N polling pulses are received from the synchronizer 18 at exactly, but the calculated times of occurrence of the envelope of the compressed radio pulses from each DPS carrier frequency (FIG. 3g). The envelopes of the compressed radio pulses from interference, whose frequencies do not coincide with the carrier frequencies of the DPS radio pulses, are located between the synchronizer polling pulses, are not passed through the key 6 and are not taken into account in the future. Only the envelope of the compressed radio pulses corresponding to all possible carrier frequencies ft (Fig ' Z), and this is the frequency selection of DFS.

From the output of the key 6, the signal arrives at the first input of the comparator 11 and the unit 7 for generating threshold voltages. Unit 7 is designed to calculate the threshold levels for each carrier frequency of RF pulses. Switches 8 and 9, switched by a digital code (FIG, Z, 4 g) from the synchronizer 18, N blocks 10 are connected in series to the output of switch 6 and the second input of comparator I0. Since the noise falling in filter band 1, MorVT have different power, and DFS radio pulses can be subject to fading, each of the N blocks 10 calculates a threshold of ur Avalan based on sample amplitude values of the envelope pulses of the total signal power and interference only for carrier frequency f. The input of each block 10 receives samples of the total signal power and interference envelope (FIG. 3) at the time of arrival of the polling clock polling pulse of the block 10. switch 8 to the detector output. Each block 10 determines the average amplitude of the input pulses m during the integration time T .. (T ,.

c

t 1

and then

absolute threshold level which is

hanging from t; and InN2 h

The comparator, comparing the threshold levels (Figs ZZ) with the output signals of the key 6 (figs about the rear), by the difference sign makes impulse decisions about the presence of DPS radio pulses or their absence in the interval 0, (fig. Zi) Over the effect of one chirp -generator 3 pulse is made by N decisions. The output pulses of the comparator 11 are fed to the first (counting) inputs of each of the N counters 13 (FIG. 3 SC) through the pulse distributor 12, which is switched synchronously with the switches 8 and 9 from the synchronizer 18 (Fig. Ze , 4d) “Second (installation) inputs 13 block counters are interconnected and connected to the recording input of multi-register register 14, to which short pulses are received from synchronizer 18 with the period Tj (T0 Ј T). The positive front of this tthulse is the content of all the counters of block 13

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is written to register 14, and the negative front sets all counters of block 13 to the zero state0. Each counter of block 13 is an integrator and counts the pulses from comparator 11 for its carrier frequency. The counter code values are directly proportional to time signal exceeding the threshold in time T

The digital code from the multi-bit register 14 is fed to a digital matched filter 15, which subtracts the mutual correlation function of the received and reference DPS. The output signal of the digital matched filter 15 is fed to a threshold unit 16, which can be a comparator, and make decisions when exceeding of the maximum correlation function of the threshold level determined by the likelihood of a false alarm, erasure or transformation when receiving DFS “The output signal of the block 16 goes to the registering block 17,

The control of the operation of the DFS reception device is performed by synchronizing iH TiTrp 18.

The synchronizer works as follows. Short pulses from the generator 19 Sfg0 4a) are supplied to the chirp generator 3 and to the first inputs of binary counters 21 and 22, setting them to zero states, the state of the counter 21 is increased under the influence of the input to its second (counting) input pulses of the clock frequency (figo 4b) from the generator 20o. The frequency of the pulses of the generator 20 is much higher than the frequency of the reference generator 19 and determines the necessary resolution of the time-frequency conversion of the DFS. The digital code of the counter 21 is directly proportional to the time interval from the beginning of the formation of the chirp pulse of the generator 3. The decoder 23 connected to this counter generates polling pulses (Fig. 4c, 3g) for the key 6 at time points that exactly coincide with the envelopes of the compressed radio frequency pulses of DPS frequencies . At the same time, the polling pulses arrive at the counting input of counter 22, which operates on a negative front. The output code of this counter comes in.

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Claims (1)

Claim A device for receiving discrete frequency signals containing a series-connected bandpass filter, the input of which is the input of the device, a mixer, a dispersion delay line and an envelope detector, as well as a linear frequency-modulated generator, the output of which is connected to the second input of the mixer, characterized in that simplification of the device due to the exclusion of several processing channels, the key and the first switch are sequentially connected ^ 5, the second switch is connected in series, the comparator and a pulse distributor connected in series to a multi-bit register, a digital matched filter, a threshold block and a recording block, sequentially connected to a master oscillator, a first binary counter, a decoder and a second binary counter, the outputs of which are connected to the corresponding inputs of the first and second switches and pulse distributor, a generator clock pulses, the output of which is connected to the second input of the first binary counter, threshold calculation blocks, the outputs of which are connected to the corresponding the input inputs of the second switch, the counter blocks ^ the outputs of which are connected to the corresponding inputs of the multi-bit register, and the counter, the output of which is connected to the clock inputs of the counter blocks and the multi-bit register, the outputs of the first switch are connected to the inputs of the corresponding threshold calculation blocks, the outputs of the pulse distributor are connected to the inputs of the corresponding blocks of counters, the output of the envelope detector is connected to the first input of the key, the output of which is connected to the second input of the comparator., the output of the master gene the radiator is connected to the input of the linear frequency-modulated generator and to the second input of the second binary counter, and the decoder output is connected to the second key input and to the counter input. Figure 2 Ln η π ··· π π Π π · · · π t l Μ • · · η γΊ η Μ. *.? ί CL ί τπύ ² x • * · λΆ / X ι X 3 X Λ / χ J η • · " η * · " t 1) fl * · · ί . . . Χ-) • · - ο ί Η • · · • · '· ~ t π • »· π • · · t "/ · • · ♦ t π • · · π • · · t • · · © · · έ FIG. 5 Μ Ιο 'Ό