SU1619281A1 - Addressing device - Google Patents

Description

one

(21) 4637714/24

(22) 01/13/89

(46) 07.01.91. Bup. № 1

(72) A.I.Bilkov, S.E.Proshin

and V.V. Chernov

(53) 681.325 (088.8)

(56) USSR Copyright Certificate No. 1417003, cl. G 06 F 12/08, 1986.

Shevkopl with V.V. Microprocessor structures. Engineering solutions. - M .: Radio and Communication, 1986, p.44.

(54) ADDRESSING DEVICE

(57) The invention relates to computing and can be used to build high-capacity computer RAM systems. The aim of the invention is to enhance the functionality by dynamically changing the size and location of the physical memory regions. The device contains blocks 1-3 of registers, multiplexers 4, 5, block 6 comparisons, block 7 of memory of the addressing tables, adder 8. The goal is achieved by introducing new elements and connections. 3 il.

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The invention relates to computing and can be used to build computer RAM systems of large information capacity.

The purpose of the invention is to expand the functionality by dynamically changing the size and location of the physical memory areas.

Figure 1 shows the block diagram of the device; Fig. 2 is a functional block diagram comparison; FIG. 3 is an example of a block diagram of the memory of the addressing tables and examples of the tables stored in it.

The device contains a block 1 of registers, a block 2 of registers 2, -2t, a block 3 of registers 3ffl, multiplexes A and 5, a block 6 of comparison, a block 7 of memory of addressing tables, an adder 8, circuit elements 11, 11t

 and Yu, -10t comparison,

The device works as follows.

The Reset signal generated after turning on the power of the computer sets the registers of blocks 1-3 to the initial zero state (the registers for initial setup are not shown). In this case, in the address space of the computer, the initial physical area of the memory address space is activated. If it is necessary to change the configuration of the placement of physical areas in the address space of a computer, the following information is entered in the registers of blocks 1-3: in the registers of block 1, respectively, the initial addresses A W)% (, m) of logical regions of the address space of the computer; the registers of block 3 are, respectively, the end addresses A ", (i of the 17th) logical regions of the address space of a computer; and the registers of block 2 are respectively the basic physical addresses A (i 17g) of the physical memory areas activated in the logical addresses of the same name simple, computer ranks. Writing to the registers of blocks 1-3 by applying to the recording inputs of the registers of the blocks, respectively, recording signals zap, n1 - zap.ntp, zap.k - zap.ktch, zap.61 - zap.bgS Recorded information in the registers goes to their inputs from the device information entry.

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When an n-bit logical address A is supplied to the address input of the device, it is converted to an n + r-bit physical address of the AP memory, depending on the installed distribution of the physical memory areas in the address space of the computer.

Upon receipt of the current Ad at the first input of the comparison unit 6, the number of the logical memory area in the address space of the computer to which this Ad value belongs is determined. For this, a comparison is made of the value of A, with

Ai, (

and a c | each

i-th (i 1, tn) logical area of the address space of a computer. At the same time, at the outputs of the comparison circuits 9 of the first group and 10, of the second group, single signals appear, respectively

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and A l Ј A | J. Address codes go to the first inputs.

, and 10, comparing the outputs of the corresponding register-corresponding schemes 9

neither

Ditch 1, and 3, blocks 1 and 3. The address code Ad is fed to the combined second inputs of the comparison circuits 9 and 10. When the value of A d hits the i-th logical area of the address space IT, respectively, at the outputs of circuits 9 J and 10, the comparison and the element 11, a single signal arises. In this case, the outputs of the remaining elements And 11 present zero signals. Thus, the unitary position code of the logical area number of the computer address space is compared at the outputs of the block b. This code goes to the inputs of block 7, at the corresponding outputs of which a memory access indication signal is generated, a binary code of the logical area number of the computer’s address space and the code of the physical-domain overlap coefficient of the memory address space in the given logical domain of the computer’s address space.

i

Fig. 3a-3r shows the truth tables of the output signals of block 7 (Fig. 3a), where a, b, c, d are signals of the unitary code of the logical area number; e, g - signals of the binary code of the logical area number; d - memory access indication signal; and, k - signals of the code of the overlap coefficient of physical regions. The -and sign is arbitrary or

indifferent logical states of the corresponding signals,,

In accordance with the truth table (Fig. 3g), the signal g occurs only if Ad falls into one of these logical areas of the computer's address space. The signals for, and the overlap code indicate the presence of an overlap in the physical areas of the memory and its nature. This information is auxiliary, for example, for a computer operator. At the intersection of several physical regions in the address space of a computer (Fig. 36), the binary number code of the upper logical domain is formed at the outputs of block 7, i.e. having the highest number (priority), From the outputs of block 7, the binary code of the logical area number goes to the address inputs of multiplexers 4 and 5, to the control inputs of which the memory access indication signal is also output from it. With a single value of this signal, the passage from the outputs of registers 1j and 2 {is solved, through multiplexers 4 and 5, respectively, the codes A..J and Ah, which arrive respectively at the subtracting and first summing inputs of the adder 8.

Code A is fed to the second summing input of the adder 8. As a result, an n + r-bit code A is formed at the outputs of the adder according to the following formula:

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Ad-AM1Atf Formula of Invention

The addressing device containing the first multiplexer and the first block of registers, and the information inputs of the registers of the first block are connected de connected to the output of the selectable number

to the informational input of the device, the inputs of the initial setup of the registers of the first block are connected to the input of the initial installation of the device, the output of the Kth register of the first block is connected

the logical area of the memory block of the addressing tables, the output value of the overlap coefficient of the memory areas of the table memory block is connected to the output of the overlap coefficient

to the K th information input of the device.

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multiplexer (K 1,, where m is the number of addressable memory areas), the IC-ro register input of the first block is connected to the K th input of the first group of the device, characterized in that, in order to extend the functionality by dynamically changing the size and location of the physical memory areas, two register blocks, a multiplexer, a comparison block, a memory block of the addressing tables, and an adder are entered into it, the information input and the input of the initial setup of the device are connected respectively to the information th inputs and inputs of the initial installation of the registers of the second and third blocks, the write inputs K x registers of the second and third blocks are connected respectively to the K input inputs of the second and third groups of the device, the output of the K th register of the second block is connected to the K th information input the second multiplexer, the outputs of the first and second multiplexers are connected respectively to the subtracting and to the first summing inputs of the adder, the output of which is connected to the output of the physical address of the device, the outputs of the first registers of the first and third blocks are connected respectively to the Km information inputs of the first and second groups of the comparison block, the input of the logical address of the device is connected to the second summing input of the adder and to the third information input of the comparison block whose output is connected to the address input of the address table memory block whose memory is connected to the strobe inputs of the first and second multiplexers, whose address inputs are

connected to the output number selectable

the logical area of the memory block of the addressing tables, the output value of the overlap coefficient of the memory areas of the table memory block is connected to the output of the overlap coefficient

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Claims (1)

Claim An addressing device containing a first multiplexer and a first block of registers, wherein the information inputs of the registers of the first block are connected to the information input of the device, the inputs of the initial setting of the registers of the first block are connected to the input of the initial installation of the device, the output of the K-th register of the first block is connected to the K-th information the input to the summing input of the adder and to the third information input of the comparison unit, the output of which is connected 40 to the address input of the memory block of the addressing tables, the output of the indication indication I am connected to the memory of the gate inputs of the first and second multiplexers, the address inputs of which are 45 connected to the output of the selected logical area number of the memory block of the addressing tables, the output of the value of the overlap coefficient of the memory areas of the table memory block is connected to the output -indication of the coefficient of overlap of the device. a δ 3 g e 0 0 0 0 X 1 0 0 0 0 0 to 1 0 0 0 1 * g 1 0 1 0 * 36 * 1 1 1 Q δ 3 g to and 0 0 0 0 0 0 One unit 3 line 0 0 Ze units q line 0 1 Three units of δ row 1 0 Four units 8 row 1 1 a δ 3 g d 0 0 0 0 0 ' to if * if 1 Fig.Z