SU1617667A1 - Device for receiving multiple-frequency signals - Google Patents

Abstract

The invention relates to a technique of wired and radio communications, and can be used as a decoding device for receiving interaction tones. The aim of the invention is to increase the noise immunity by eliminating the pickup from the harmonics of the received frequencies. The device contains a clock generator 1, a divider 2 with a variable division factor, a driver 3 switching signals, a band-pass filter 4 with switched capacitors, a counter of 5 states, a block 6 for changing the division factor. The goal is achieved by the introduction of threshold blocks 8 and 11, an amplifier-limiter 7, a decisive block 9 and a block 10 receiving fixation. 2 Il.

Description

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The invention relates to a technique of wired and radio communications and can be used as a decoding device of radio stations, in the control equipment of telephone exchanges and devices for remote control of various objects.

The aim of the invention is to increase the noise immunity by eliminating the pickup from the harmonics of the received frequencies.

; FIG. 1 shows a structural electrical diagram of a device for receiving multi-frequency signals; FIG. 2 shows the possible implementation of a shaper of 3 switching signals.

The device for receiving multi-frequency signals contains a clock generator 1 divider 2 with variable division factor, shaper 3 switching signals, band-pass filter 4 with switched capacitors, 5 states counter, block 6, changes division factor, limiting amplifier 7, second threshold block 8, decimal block 9 , block 10 receiving fixation, the first threshold block 11 binary counter 12, multiplexer 1h element AND-NOT 14, element AND-NOT 15 whose output is connected to the first input of the resolver 9, the second input of which is connected It is not connected with the second output of the switching signal generator J, and the output of the resolver 9 is connected to the control input of the receive latching node 10, the information input of which is connected to the output of the second threshold element 11 whose input is connected to the output of the bandpass filter 4 s switched capacitors, and the output of the receive latching unit 10 is connected to the second input of the state counter 5 and is the output of the device.

A device for receiving multi-frequency signals operates as follows.

In the initial state, there is no low frequency signal at the input of the device. At the same time, at the output of the amplifier-limiter 7, the threshold unit 8, the band-pass filter 4 and the threshold unit 11, there are no signals either. The divider 2 under the action of clock pulses from the clock generator 1 sequentially translates the counter 5 states across all expected positions of input frequencies.

The selection time of each of the expected frequencies is set by divider 2. Counter 5 sets the division factor through block 6 of the change of the division factor of the divider r, which generates frequencies that are multiples of the probable input signals and sends them to the driver 3 signals

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commutation. The imaging unit 3 tunes the band-pass filter 4 in the frequency band. Solving unit 9 is designed to compare the input signal frequencies from the output of the threshold unit 8 and the switching signals from the shaping device 3. The device generates a control signal at its output only if during the period of the expected input signal with a duration of 10 It is supplied from the output of the threshold block B with no more than one voltage (front) differential.

As a decision block 9, a binary counter counter can be used — its input is connected to the output of threshold block 8, and the reset input to the output of driver 3,

The receive latching unit 10 is designed to form a logical signal of a device arriving at the output and a counter 5 states in the presence of the enable signal from the decision block 9 and clock signals (fronts) from the output of the threshold block 11 at its inputs.

5When the device enters the input

a low-frequency signal that does not coincide in frequency with the expected one, this signal is amplified by the limiting amplifier 7, and the threshold unit 8 forms from it a pulse 0 sequence arriving at the receiving unit 9.

Solving unit 9 at the frequency of the input signal up to 2 FO forms allowing P 10 receive latching. However, 5 receiving receive block 10 does not generate a receive signal because its input does not receive a signal from the series-connected band-pass filter 4 and the threshold block 11 for the reason that the frequency of the low-frequency signal at the device input and the frequency of the expected signal do not match. The divider 2 frequencies after the expiration of the time interval for analyzing the input frequency transfers the counter of 5 states to the second position (corresponding to the code of the second frequency). In this case, the division ratio of the divider 2 frequency is changed through the block b of the variation of the division ratio. The device is ready to receive the second assumed frequency, set by the driver about the switching signals.

If these frequencies do not match, the 5-state counter is transferred to the third state, etc., until a signal of the expected frequencies is received. To minimize the frequency polling time, the 5 state counter must have a number of states equal to the number of received signals.

When the frequency of the input signal coincides with the frequency of tuning the band-pass filter 4, the signal of the corresponding frequency is generated at the output of the latter, which through the threshold unit 11 enters the clock input of the receive latching unit 10.

With a delay of one (or more) period of the input frequency at the output of the receive latching unit 10, a logical signal is generated that a corresponding tone frequency signal is present, outputted by the device for recording and blocking the change in the state of the 5 state counter. A delay for one period of the input frequency (or more than a certain time, for example, the maximum period of all expected tones) is necessary to avoid triggering when a signal arrives at the device input more than what is expected (for example, harmonics), since the decisive block 9 still did not generate a control signal.

Such a construction of the device makes it possible to exclude the possibility of receiving tonal signals of multiple frequencies (harmonics).

The imaging unit 3 may be implemented as a serially connected binary counter 12 and a multiplexer 13. The reset signal of the binary counter 12 and the control of the decision block 9 is generated by AND-HE elements 14, 15.

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Claims (1)

The formula of the device for receiving multi-frequency signals, comprising a series of connected clock generator, a divider with a variable division factor, a state counter and a block for changing the division factor, the output of which is connected to the second input of a divider with a variable division factor, the second output of which is through the signal conditioner The switching is connected to the first input of a band-pass filter with switched capacitors, characterized in that, in order to improve noise immunity by eliminating triggers from the harmonics of the received frequencies, the first threshold unit and the series-connected limiting amplifier, the second threshold unit, the decision unit and the receive latching unit, the output of which is connected to the second input of the state counter, are entered and is the output of the device for receiving multi-frequency signals, whose input is The input of the amplifier-limiter, the output of which is connected to the second input of a band-pass filter with switched capacitors, the output of which through the first threshold unit is connected to the third input b the receive hold lock, and the second output of the switching signal generator is connected to the second input of the decision block. block 3