SU1613969A1 - Spectral analyzer - Google Patents

Abstract

The invention relates to a measurement technique, in particular to the measurement of the characteristics of random signals. The aim of the invention is to improve the accuracy of the analysis. The analyzer contains input amplifier 1, analog-to-digital converter 2, digital filters 3 ₁ ... 3 _N , buffer registers 4 ₁₁ ... 4 _1N and 4 ₂₁ ... 4 _2N , digital peak detector 5, indicator 6, digital switch 7, a logarithmic converter 8, a square root extraction unit 9, a digital switch 10, a detection unit 11, a random access memory 12, a decoder 13, a priority interrupt unit 14 and a control unit 15. 2 hp ff, 2 ill.

Description

one

(21) 433523А / 21-24

(22) 27 „11„ 87

(46) December 15, 90 Bylo No. 46 (72) AoAo Smelters (53) 621.317 (088.8)

(56) USSR Copyright Certificate No. 1308927, cl. G 01 R 23/16, 1984,

(54) SPECTRAL ANALYZER

(57) The invention relates to a measurement technique, in particular to the measurement of the characteristics of random signals. The aim of the invention is to improve the accuracy of the analysis. The analyzer contains an input amplifier.

1, analog-to-digital converter

2, digital filters 3j | -3f, buffer registers 4 ,. „.4,„ and f .int DIGITAL peak detector 5, indicator

6, digital switch 7, logarithmic converter 8, square root extraction unit 9, digital switch 10, detection unit 11, random access memory 12, decoder 13, priority interrupt block 14. and control unit 15, j Cp. f-ly, 2 ill.

(L

O5

(O5 CO

d 28 7 "S 6 15

II 3 Ji P in

1 11G I 1ТТ

Shig.1

i

The invention relates to a measurement technique, in particular to the measurement of the characteristics of random signals,

The purpose of the invention is to improve the accuracy of the analysis.

FIG. 1 shows a spectral analyzer; FIG. 2 is a digital peak detector;

The analyzer contains input amplifier 1, ADC 2, third-octave three-octave filters 3, j | -3 | j buffer registers 4, and Aj. 5 1SCRUPER peak detector 5, indicator 6, digital coma 7, logarithmic converter 8, square root extraction unit 9, digital switch 10, block 20

detection 11s random access memory 12, decoder 13 ,, priority interrupt block 14 and control unit (CU) 15 An analyzed signal is fed to the input of amplifier 1; the output of the switch 7 receives the codes of the maximum or root-mean-square values of the signal in the corresponding 1SP-1x frequency bands; The inputs of the control unit 15 of the analyzer are supplied (from the keyboard on the front panel of the analyzer or from the output of an external control device, for example, a computer), respectively, the coefficient of the factor 35 and the signal amplification, the pulse of the analyzer, the pulse, the beginning of the output of the measuring information. The output of the analyzer is given a pulse, signaling the end of the output process, and information. The fifth and sixth inputs of the analyzer are supplied with potential signals that determine, respectively, the type of measuring information arriving at output 45 of the analyzer (maximum or SCR analyzes the current signal) and its scale (linear or logarithmic). The input 16 is connected to the input of the amplifier 1 "The output of the amplitude-Q bodies 1 is connected to the input of the ADC, 2, the output of which is connected to the inputs of the filters, the output of each filter-. 3J is connected to the inputs of two corresponding buffer registers 4 and 4i, the output of each register 4 ,, is connected by a sapper input, and the register 4 2 is connected to the second input of the detector 5, the output of which is connected to

the input of block 11, the output of which is connected to the input of block 9 P. the first input of KOMi i TaTopa 10, the second input of which is connected to the output of block 9, and the output to the input of the converter 8 and the first input of switch 7, the second input of which is connected to the output the converter 8, and the output with the input and the control unit output 17, the inputs of the seventh, eighth, third and fourth unit 15 are connected respectively to the first, second, third and fourth inputs of the control unit 15, the output 22 is connected to the twelfth output, and the inputs of the fifth and sixth to the fifth and sixth inputs of the control unit 15, the first output of which connected to the first control input of the unit 11 and the control input of the co-switch 10, the second output of the control unit 15 is connected to the control input of the converter 8, the control output of the unit 11 is connected to the first input of the control unit 15 and the first control input of the RAM 12, the second control input which is connected to the third output of the control unit 15, the fourth output of which is connected to the second control unit, and the input of the unit 11, the third control input of which is connected to the third control input of the RAM 12 and the fifth output of the control unit 15, the sixth and eleventh outputs of which are connected accordingly with the control inputs of block 9 and detector 5, the control output of which is connected to the ninth input of the control unit 15, and the control input of the decoder 13, each and every three outputs, which is connected to the control inputs of the corresponding register 4 j and 5, the seventh output of the CU 15 is connected to the code of the block 14 and to the inputs of the decoder 13 and the RAM 12, the input - output of which is connected to the input - output of the block 11, the eighth output of the CU 1 connected to the control input of the block 14, each of the inputs of which connected to the control 1m with the output of the corresponding register 4 j The input of which is connected to the control output of the corresponding register (, the control output, unit 14 is connected to the second input of the control unit, the fifth, ninth, tenth and eleventh outputs of which are connected to the control inputs of the A / D converter 2 and amplifier 1, respectively, the thirteenth output The control unit 15 is connected to the control input of the switch 7.

5.6

The detector 5 (FIG. 2) contains a multiplier 16, a ROM 17, delay elements 18, 19, and 20, and a division block 21. The first input of the detector 5 is connected to the first inputs of the division blocks 21 and multiplication 16, the second input of the detector 5 is connected to the second input of the division block 21, the output of which is connected to the input of the ROM 17, the output of the ROM 17 is connected to the second input of the multiplication unit, the output of which is connected to the output of the detector 5, the control input of which is connected to the control input of the division unit 21 and. the input of the delay element 18, the output of the delay element 18 is connected to the control input of the ROM 17 and the input of the delay element 19, whose output is connected to the control input of the multiplication unit 16 and through the delay element 20 to the control output of the detector 5o

The analyzer works as follows.

Before the analysis is started, the analyzer is programmed. In this case, the signal amplification factor codes and the time of its averaging are fed to inputs 7 and 3. The output of the measurement information is carried out at the end of the analysis by applying the trigger pulse to input 4. The type of output measurement information (maximum or RMS signals) and the scale (linear or logarithmic) of its presentation are determined by the signals supplied to inputs 5 and 6. End of the output process measurement information is recorded by a pulse arriving at the output 11 of the analyzer.

The corresponding gain of amplifier 1 is set by the code received from the tenth output of the control unit (CU) 15 (operation of CU 15 will be discussed below) The amplified and frequency-limited top signal from the output of amplifier 1 is fed to the input of ADC 2, from which filter inputs, codes are received, selective values of the signal. ADC 2 is triggered by pulses from the ninth output of the control unit 15, the signals at the outputs of the third-octave filter are referred to as

139696

narrowband and represent amplitude-modulated (AM) oscillations with a carrier frequency equal to g the average frequency of the passband of the filter. The maximum values and the RMS of the indicated signals can be determined through the amplitude values of the last signals. At the same time, the RMS of the AM signal is calculated by the following formula

SKZ 0.707

u

(one)

15 where a- - i-oe amplitude value

AM signal; n is the number of amplitude values

AM signal and maximum value determined

20 as the largest in magnitude amplitude value of the AJI signal. The signal at the output of each digital filter is represented by the YUTSIM time series (sequence of codes of the instantaneous values of the filtered signal). The sampling frequency of each of the specified series is determined by the average frequency of the frequency response. appropriate filter

30 ra, and, as a rule, twice the last

To determine the parameters in the intended analyzer, the signal at the output of each filter 3, on

 Each of the half-periods of oscillation is represented by two samples shifted relative to each other by a quarter of a period (the signal sampling frequency exceeds the average frequency of the AFC period of the corresponding filter by four times the Q) The samples from the output of each filter 3 are sequentially recorded into two corresponding registers 4 ,, and. t which are multi-mode buffer registers. These registers, depending on the signal arriving at their control inputs, operate Q in the information recording mode or its

- issue. To write data to the register 4,;, it is also necessary to have a difference in the sign bits of the incoming and stored codes, and to write the data to the register, a destructive signal from the control output of the register 4, is necessary. Thus, the first sample in each half-period of the output signal of the filter 3J

is written to register 4,. After writing the specified code to register 4-, an interrupt request signal is generated at its control output, which in this case is permission to write the next code to register A. 2. After writing the next code to register 4.2. the control output of the latter generates a request signal on the interrupt, which in this case is a request for processing. The signals from the control outputs of the .4п2 registers. each arrive at the corresponding 5 input block of 14 priorities. The main function of unit 14 is to receive signals from the control outputs of registers 4. A2 recognition and identification of control signals. Since processing requests are generated independently of each other, to establish the order of their satisfaction, each of the registers 4 and 2 is assigned a priority of 25, according to the carrier frequency of the signal whose samples are written to it. The highest priority is given to the register receiving the signal samples with the highest carrier frequency itself. At the output of block 14 a code of the channel currently being served is formed, and on its control code there is a tracking impulse. The specified code goes to the corresponding inputs of the RAM 12, the number of cells which is equal to the number of analyzer filters, and the decoder 13 and is, with respect to these devices, the address code Depending on Q code on the input of the decoder. 13, a signal is formed at one of the outputs of the latter, which translates the corresponding pair of registers 4 j and 4 from the receive mode to the mode of information output. At that, the output gates of these registers are transferred and from the passive high resistance state to the active state and information stored in these registers, along two corresponding data lines, is fed to the first and second inputs of detector 5. The launch of detector 5 is effected by a pulse coming 1m to its control input from the twelfth output of control unit 15. The indicated pulse formed when the second input of the CU 15 arrives, the pulse from the control output of the unit

50

55

0

five

14 o Detector 5 takes two samples taken during one half-period of the signal, calculates the amplitude value of this half-period. After the calculation process is completed, detector 5 generates a corresponding code on its code and a pulse on the control output. This pulse arrives at the ninth input of the control unit 13 and, at the control input of the depressor 13, the enable signal from the corresponding code of the decoder 13 is removed, and the corresponding pair of registers 4 and 4 of the viyachi mode is switched to receive information about the output gates of the specified registers switched to high impedance mode and disconnected from the corresponding data trunks. At the same time, at the fifth output of the CU 15, an impulse is generated at the third input of RAM 12 and the third entrance of the detector 11. This impulse reads the contents of the cell of RAM 12 determined by the code at the input of the latter, and writes it to the detector 11c , At the same time, the code from the output of the detector 5o is recorded in the detector 11. In the detector 11, if there is a permitting signal arriving at its second input from the fourth output of the control unit 15, the incoming data is processed. output detector 5 is determined by the maximum value and the current value of the sum of squares of the signal samples. After the elementary processing cycle, the detector 11 forms at its control output a pulse that arrives at the first input of the control unit 15 and at the first input of the RAM 12o. The processing results from the detector 11 are re-. written into the previously selected RAM cell 12 (the first group of bits in each cell of RAM is allocated for the maximum value code, the second group for the current value code of the sum of squares of processed values and the third group for the number of signal values processed) In addition, on the second The output of the CU 15 generates a signal permitting the block 14 to service the next pair of registers. The described processing continues until the end of the predetermined signal averaging time. The process of outputting the analysis results is started

It comes from the supply of input 4 of the analyzer and further to the fourth input of the CU 15 pulse signal. At the same time, at the seventh output of the control unit 15, the address code of the first cell of RAM 12 is formed, and at the fifth output, a pulse o. This impulse reads the contents of the first cell of RAM 12 and writes it to detector 11. At the same time, depending on the signal on the first control The input of the detector 11 at its output is given a code of the maximum value or the average value of the square. If the maximum value is output, in accordance with the control signal, the switch 10 passes the code to its first input to the output. If the RMS is output, then the code to the second input from the output of unit 9 passes to the output of the switch 10. Block 9 is a ROM, the cells of which contain the values of the square root of the codes received at its input, multiplied in accordance with (1) by the value 0.707. The codes at the input of unit 9 are the codes of the address of its cells, and the impulse arriving at its control input is a read signal of the contents of the selected cell. The specified impulse is generated at the sixth output of the CU 15 after the end of the impulse at its fifth output. Thus, depending on the signal at the control input of the switch 10, its RMS code or maximum values will be output at its output. The specified code is fed to the input of the logarithmic converter 8 and to the first input of the switch 7. The converter 8 is a ROM, the cells of which contain logarithm values of the codes inputted to its input. The codes entering the input of the converter 8 are the address codes of its cells and the impulse arriving at its control input is a signal to read the contents of the selected one. These impulses are formed at the second output of the CU 15 at the end of the impulse at its sixth output. Depending on the signal at the control input of the switch 7, its output will receive the code of the selected signal value in a linear or logarithmic scale. If a linear, data presentation scale is used, then the output

ten

switch 7 passes the code from its first input. If a logarithmic scale is used, then the output of the switch 7 passes the code posting to its second input from the output of the converter B. From the output of the switch 7, the code goes to the indicator 6 and the output of the analyzer 17. At the same time,

the first cell of RAM 12 is terminated. The output of the contents of the second, third, and so on. The RAM cells 12 is performed sequentially in accordance with the above description. At the same time, at the seventh output of the control unit 15, the address code of the corresponding cell is generated each time.

The detector 5 (Fig. 2) works as follows.

This block calculates the current amplitude values of the signals from the outputs of filters 3 (, - 3 ". Each half-period of the signal at the output of each filter is represented by two counts shifted relative to each other by a quarter of the period, the indicated counts are represented by the expressions

thirty

ji wtj (j, (2)

7

i jmsi (wtj + |) xj.sin (o ;; +

(3)

+ 5 -xj cosCe,

where x | and xj2 are the first and second counts of the j-ro papuperiod

signal; j M a small value

j-ro half cycle; t j is the moment of sampling of the first reference of the j-ro half-period relative to the start of the last “

To calculate (.2) or (3) -. it is necessary to determine the value. l is enough to divide (2) by U)

2i SiusiS j. t., f.)

X .. x: ..

Xj j,

From Of arctg 2i

J-K.,

5iL.

(five)

x

Using (2, and (5), we get JM GT; T g)

JM sinO (fT. Г, .xib Л isin arctg (---)

L) 2. J

Thus, by two readings, using (6), one can determine the amplitude value of the j-ro half-period.

eleven

1613969

The described processing algorithm is implemented in detector 5 as follows: The codes for the values of xj, which are fed to the first input of detector 5, are then fed to the first inputs of blocks 21 and multiplication 16 ,,. Codes of xjg values arriving at the second input of detector 5 are further fed to the second input of block 21. Detector 5 starts. A pulse arrives at its control input. This pulse starts division block 21. Upon completion of the division operation, the output code 21 is formed at the output of block 21. input values in accordance with (4). This code using the ROM 17 is subjected to a functional transformation. In this case, a function is implemented

fj "

one

(7)

sin arctgCXj, / xj) j

For this purpose, for all possible values of the ratios xjj / xj, the values of the function (7) are calculated and written into the corresponding cells of the ROM 17. The code entering the ROM 17 from the output of block 21 is the address code and selects the corresponding ROM cell. In this case, the read signal of the contents of the selected cell is fed to the ROM 17 from the output of element 18, which provides a delay of the signal by the time required to execute the division operation by block 21 "The content of the selected cell of the ROM 17 goes to the second input of the block 1 times 16 arriving at its first and second inputs on a signal coming from the output of element 19 This circuit delays the signal arriving at its input for the time of transients arising from the reading of information from ROM 17. After the end of The multiplication steps at the output of block 16 generate the amplitude code of the current half-period of the output signal of the filter 3 ;. This code arrives at the output of the detector 5o. At the same time, the control code of the detector 5 receives a signal from the output of element 20, which delays the signal arriving at its input for the duration of the multiplication operation by block 16. This signal fixes the end of the data processing cycle with the definition of the current 1 amplitude value of the signal.

about rmu l and

f

12 inventions

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five

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five

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Claims (2)

1. A spectral analyzer containing an input amplifier, whose input is connected to the analyzer's input, an analog-to-digital converter, a detection unit, the input-output of which is connected to the input-output of the random access memory, the square root extractor, the output of which is connected to the first input of the digital switch , a logarithmic converter, an indicator, the input of which is connected to the output of the analyzer, a decoder, the input of which is connected to the input of a random access memory and the output of the block when routine interrupts, wherein the first output of the control unit is connected to the control input of the digital switch and the first input of the detection unit, the second to the control input of the logarithmic converter, the third to the first governing input of the random access memory, the fourth to the second control input the detection unit, the fifth with the third control input of the random access memory of the detection unit, the shield with the control input of the square root extraction unit, the seventh with decoder and random access memory inputs, the eighth with the control input of the priority interrupt unit, the ninth with the control input of the analog-digital converter, the tenth with the control input of the detector, the control output of the detecting unit is connected the second control input of the random access memory and the first input of the control unit; the contact output of the priority interrupt unit is connected to the second input of the control unit; the eleventh output of the control unit is connected to The installation output of the device, the third to seventh inputs of the control unit are connected to the installation inputs of the device, characterized in that, in order to improve the accuracy of the analysis, digital filters, 2 buffer registers, a digital peak detector, a second digital switch, an additional control are entered into the jiero yu 1316 input, while the output of the input amplifier is connected to the input of an analog-to-digital converter, the output of which is connected to the combined inputs of digital filters, the output of each filter is connected to the inputs of the corresponding pair of buffer registers, the control inputs of which are connected to the corresponding output of the decoder, the control output the first register of each pair is connected to the second control input of the second register of the same pair, the control output of which is connected to the corresponding input of the priority interrupt block, the outputs of the first and second inputs of the peak detector, the output of which is connected to the input of the detection unit, the control, the input of the peak detector is connected to the twelfth output of the control unit, the eighth input of which is connected to the auxiliary control input of the analyzer, the control the input of the peak detector is connected to the ninth input of the control unit and the control input of the decoder, the output of the detection unit is connected to the input of the square root extraction unit and the second th input of the first switch, the output of which is connected to the first in 10 396914 the second switch and the input of the logarithmic converter, the output of which is connected to the second input of the second switch, the output of which is connected to the output of the analyzer, and the control input to the thirteenth input of the control unit, 2. The analyzer according to claim 1, characterized in that the peak detector is made in the form of a division unit, a multiplication unit, a persistent storage device and three delay elements, the first detector input connected to the first inputs of the division units and the multiplication, the second detector input is connected to the second input of the division unit, the output of which is connected to the input of a permanent storage device, the output of which is connected to the second input of the multiplication unit, its output connected to the output of the detector, the control input of which is connected to 25 The control input of the split unit is the input of the first delay element, the output of which is connected to the control input of the persistent storage device and the input of the second delay element, the output of which is connected to the control input of the multiplication unit and through the third delay element with the control output of the detector. 15 20 thirty