SU1607013A1 - Address shaper - Google Patents

Abstract

The invention relates to computing and microelectronics and can be used in the design of persistent storage devices. The purpose of the invention is to expand the field of application of the imager by generating a sampling signal at several addresses. This is achieved by the fact that each memory element 1 of the driver contains a second memory transistor 4. The low threshold voltage of both transistors 3, 4 simultaneously provides a low level signal from both outputs of memory element 1. As a result, the comparison unit 2 generates a sampling signal at the output 6 with an arbitrary address code at the inputs 5 corresponding to the given memory element 1. 1 il.

Description

The invention relates to computing and microelectronics, in particular, to semiconductor integrated circuits, and can be used in the design of permanent storage devices (ROM). The purpose of the invention is to expand the functional capabilities of the driver by generating the Sampling signal at several addresses.

The drawing shows an electrical diagram of the former.

The address driver contains 15 memory elements 1, a block 2 comparison. The address is stored in the first- and second storage transistors 3, 4 of the memory elements 1. Inputs

The first group of Comparison Hall 2 is the address inputs 5 of the driver and the output is output 6 of the driver. In addition to the storage transistors 3, 4, the memory elements 1 consist of two load transistors 7, a key transistor 8.

The forming body works as follows.

The greatest gain comes from the use of a former in computational zo systems, which include ROM inputs with a masked method of entering information, i.e. entry of information in. ROM manufacturing process. In this case, the address shaper is placed on the same chip with the ROM and is programmed at the same time and in the same way as when entering information into the ROM drive. The most common way for Q to enter information into a memory drive is by varying the threshold voltages of the drive's transistors. At the same time, each of the transistors 3, 4 is manufactured with a threshold voltage 45 which exceeds or is significantly lower than the supply voltage. At the same time, a low threshold voltage can have a transistor 3, or a transistor 4, or transistors 3 and 4 simultaneously, which corresponds to the states of the memory element 1 of Log.1, Log.O, or an indifferent state. In the latter case, the signal at output 6, allowing access to the ROM, will be generated with any address code on input 5 of this memory element 1.

If the threshold voltage of the transistor 3 is lower than the supply voltage, then

35

0 5

about Q 5 0

five

its current and the input of the block 2 connected to the drain are in the Log.O state, and the drain of the transistor 8 is in the LogL state if the threshold voltage of the corresponding transistor 4 exceeds the supply voltage. If the threshold voltages of both the transistor 3 and transistor 4 of this memory element 1 are lower than the voltage of the power source, then both outputs of this memory element and the inputs of block 2 connected to them are in the Log state. ABOUT.

The address code received at the inputs 5 is compared in the comparison block 2 with the expected stored in the block of elements 1. In the case of coincidence of the indicated codes, an enabling signal appears at the output 6 of the device (selection signal, ROM). If an indifferent state is stored in one or several elements 1, then the enabling signal at output 6 is independent of the code on the corresponding inputs 5.

Claims (1)

Invention Formula The address driver containing the comparison unit, the output of which is the output of the driver, the inputs of the first group are the address inputs of the driver, memory element 1, each of which consists of two load transistors, a key transistor and the first storage transistor, the source of which is connected to the source of the key transistor. transistor and is connected to the zero potential bus of the driver, and the drain is connected to the gate of the key transistor, with the corresponding input of the second group of the comparison unit and to the source of the first load transistor, the drain of which is connected to the drain of the second load transistor and connected to the driver's power supply bus, the source of the second load transistor is connected to the drain of the key transistor and with the corresponding input of the second group of the comparator unit, in order to expand the field of application shaper due to the formation of a sampling signal at several addresses, it contains in each memory element a second memory transistor, the drain and source of which are connected to the drain and the source, respectively o key transistor. 1607013. and the gate is connected to the gate of the first transistors, the gates of which are connected to the memory transistor and the drain from the sources of the first and second upper and second transistor load transistors, respectively.