SU1594645A1 - Automatic controller of capacitor bank - Google Patents

Abstract

The invention relates to electrical engineering and is intended to regulate the power factor of electrical installations using capacitor banks. The goal is to increase the control accuracy and simplify by adjusting, depending on the signal, proportional to the difference of the total current of the network and its active component, i.e. I m (1-COSϕ). For this purpose, a two-input logic element AND 6, two triggers 9, 10, a two-input logic element OR 12 are added to the controller, forming a pulse, controlling key 5 when the current and voltage signs do not match. The control signal is measured by digitally integrating the current in the mismatch of the current and voltage signs using two frequency-pulse converters 7, 8 and a reversible counter 11. Switching sections of a capacitor battery is carried out depending on the number recorded by the reversing counter using a programmer 13 and a switch 14. 2 Il.

Description

The invention relates to electrical engineering and is intended to control the power factor of electrical installations using capacitor banks.

The purpose of the invention is to improve the accuracy of regulation and simplification of the device.

Figure 1 shows a functional diagram of an automatic regulator of a capacitor bank; in FIG. 2 - timing diagrams explaining the operation of the regulator. ·

The automatic controller of the capacitor bank contains a voltage converter 1, a current converter 2, the first 3 and second 4 comparators, a controlled key 5, a two-input logic element And 6, the first 7 and second 8 frequency-pulse converters, the first 9 and second 10 Triggers, reversible binary counter 11, two-input logic element OR 12, the programmer 13 and the switch 14 sections of the capacitor bank,

The TV output of the voltage converter 1 is connected to the first input of the comparator 3, the second input of which is combined with the second input of the comparator 4 and connected to the zero potential bus. The output of the current converter 2 is connected to the first input of the comparator 4, the output of which is connected to od. from the inputs of the logical two-input element Ibi with the T-input of the T-trigger 10. The output of the comparator 3 is connected to the other input of the element And 6 and the input of the T-trigger 9. The K-inputs of the first and second T-triggers 9 and 10 are combined and connected to the output of the element And 6, and the outputs are connected to the corresponding inputs of the two-input element OR 12, the output of which is connected to the control input of the controlled key 5. The inputs of the pulse-frequency converters 7 and 8 are combined and connected via the controlled key to the output of the current converter 2. The output of the pulse-frequency converter verters 7 is connected to an input summing binary down counter 11, and the output pulse-frequency converter 8 - with its subtraction input. The outputs of the counter 11 are connected to the outputs of the programmer 13, the output of which is connected to the input of the switch 14 sections of the capacitor bank.

Automatic regulator of the capacitor bank operates as follows.

At the output of the converter 1, a signal is generated and, proportional to the voltage and = TsjhpyL phase of the electrical network, which is fed to the first input of the comparator 3. At the output of the latter, a pulse train is formed (Fig, 2).

where 1F _e = co8 £ - the signal corresponding to the logical level ”1,

A signal of 11 _g is formed at the output of the primary current converter 2, proportional to the current g = T _m 51p (<cs - <() of the phase of the electric network, which is fed to the first input of the comparator 4, at the output of which a pulse sequence is formed

Ir for ΐ> 0; 0 for ί 0.

Comparators 3 ή 4, two-input logic element AND 6, two T-flip-flops 9 and 10, two-input logic element OR 12 are a logical circuit for generating signals of logical 1 in case of mismatch

signs 1 signals and their: g and _g © and ₂ for t - -Ϊ- s <- t 4 ^! and r = 1 _ t ht 1 0 at -m - < r < " 9

where T is the period of the supply voltage.

. The formation of the signal and _1g is as follows.

Pulses of both ₃ and and, shifted in phase by an angle ψ, arrive at the T inputs of the first 9 and second 10 T triggers, respectively, and the leading edges set them to a single state once per period. In this case, the first T-trigger 9 is always set to a single state at the beginning of the period, and the second T-trigger 10 is at the time moment shifted relative to the beginning of the period by ΐ = ϊψ / 2'ί ?, where φ is the phase angle between current and voltage. In the case of a residual current <? ? Oh, ahead of £ <0. At the output of the two-input element And 6, pulses are formed, with pulses 1f and 11p coinciding, the leading edge of the pulses Ι) _έ sets the triggers 9 and 10 to the zero state. As a result, with a lagging current, the T-flip-flop 9 is set to a single state at ί = 0 and the air turns into a zero state at 6 =? . Setting the T-trigger 10 to a single state by a pulse coincides with the moment of setting it to zero state by a pulse at 15

C = T, Therefore, with a lagging current at the output of the second T-flip-flop 10, the signal is always 0. With an advanced current, setting the first T-flip-flop 9 to a single state by pulse 20 coincides with the moment when it was set to zero by a pulse Therefore, with a leading current of the output of the first T-flip-flop 9, the signal is always 0. The second T-flip-flop 10 25 is set to a single state at Г = Т- ί with a 1C pulse and returns to the zero state at the beginning of the next period with a pulse u ^. The pulses 1ph and ϋ _{1θ are} repeated at the output 30 of the logic element OR 12.

Thus, at the output of the logic element OR 12 in each period of the network voltage, a pulse is formed when the signs of the current and voltage do not coincide.

The pulses and _n from the output of the OR gate 12 are fed to the control input of the controlled key 5, which, when closed, connects the output 40 of the current converter 2 to the combined inputs of the first 7 and second 8 frequency-pulse converters.

Due to the fact that in the case of lagging and leading current signals 45 coming from the output of the controlled · key have different signs, the pulse-frequency converters 7th 8 have different static characteristics: 50

Κγΐφ for Φ <0; ;

⁼ [0 for and ₅ 0;

r o for u ₅ ^ o, ^£ ? [to _? and _? for and ₅ > 0, ⁵⁵ where C, £ are the output frequencies of the converters 7 and 8;

To _? , transmission coefficients of pulse-frequency converters 7 and 8, to ₇ = to ₈ .

With a lagging current, the signal from the output of the controlled key 5 has a negative sign, i.e. and _y <0. Pulse and ₅ , acting during the interval ΐ, is converted by the first frequency-pulse converter 7 into the pulse repetition rate £ _? which are fed to the summing input of the binary reversible counter 11, With a leading current signal> 0. The pulse and _{5 are} converted by the second pulse-frequency converter 8 into the frequency of the pulses that are fed to the subtracting input of the binary reversible counter 11, Therefore, is recorded in the binary reversible counter 11 the number + £ and _y for u ₅ 0;

-Up ₈ at and ₅ ? about, ? R

I and ₅ ae = K ₂ K ₇ 5 ΐ _Μ 3ϊη <ωϋ _ ΚιΚτΙμΤ.

- C>) 8s ---------- (1-co8 (p) = = ΚΙ _Μ (1 - sover), where K _{2 is} the transfer coefficient of the current transducer;

- coefficient proK ₂ K ₇ 1l, T ~~ 2 ~ 1G portion.

The number Ν ₁₇ , recorded in a 1 G binary counter, is fed to the programmer, which, depending on the number code and the switching algorithm, includes the required number of sections of the capacitor bank.

Turning sections capacitor bank increases the capacitance of the compensating current, and hence, reduction of the angle of phase displacement between current and napryazheniem.Vklyuchenie sections occurs as long as the controlled variable K1 _M (1 - so5Ts>) reaches a value smaller deadband device.

Thus, in the proposed technical solution, the regulation is carried out depending on the parameter 1 _m (1-sozf, i.e. the difference between the total current and its active component.

The deadband of the controller, necessary for discrete regulation of the reactive current, can be implemented by shifting the static characteristics of the pulse-frequency converters 7 and 8 or by the algorithm of the programmer 13.

Thus, the regulation is carried out as a function of the parameter 1 ^ (1 - soz?), Which is measured by integrating the current in the interval of mismatch between the signs of the current and voltage of one phase. Voltage asymmetry does not affect the accuracy of measuring the regulation parameter. Changes in the voltage in the electric network that are not related to changes in the reactive component of the current do not affect the accuracy of regulation of the capacitor bank, which distinguishes the proposed regulation algorithm from regulation by reactive power.

Thus, the use of a controlled key, a two-input logic element OR, an additional pulse-frequency converter, two T-tigers and two-input logic element AND in an automatic controller of a capacitor bank allows to increase the accuracy of regulation, noise immunity and simplify the design of the device.

Claims (1)

Claim An automatic capacitor bank controller comprising a voltage converter, a current converter, two comparators, one input of the first of which is connected to an output of a current converter, a pulse-frequency converter, a reversible counter, a programmer and a switch of sections of the capacitor bank connected in series, characterized in that, for the purpose of increase control accuracy with frequency deviations and phase voltage asymmetries and simplify the device; a controlled key is introduced into it, a two-input logic cue element and · two T flip-flop, two-input OR gate and a second pulse frequency converter having an input merged with the input of the first pulse-frequency converter and in a controllable switch connected to an output of the current converter, and an output connected to a subtracting input of reversible. a counter, the summing input of which is connected to the output of the first frequency-pulse converter, the first input of the first comparator is connected to the output of the voltage converter, the second input is combined with the second input of the second comparator and connected to the zero potential bus ^ the outputs of the first and second comparators are connected to the T-inputs, respectively, of the first and the second T-flip-flops and inputs of the logical element And, the output of which is connected to the combined K-inputs of the first and second T-flip-flops, the outputs of which are connected to the inputs of the logical th element OR, the output of which is connected to the control input of the control key. ρΗ π _ε ”ί _________ η 1-1 _s7 _ P P P __g / and ₅ l ΖΙ Ζ1 / ί 0 AND 1U % YaS ...... INN ι % ΙΙΙΙΙ NIN 1 * ι Figure 2