SU1594551A1 - Computer to peripherals interface - Google Patents

Abstract

The invention relates to computing and can be used to connect remote peripheral devices to the channels of computer systems. The aim of the invention is to increase speed. The device comprises a polling control unit, an information transmission control unit, a shift register unit, a request unit, a multiplexer, a transceiver unit, a group of information storage units, a group of marker extraction units, a group of signal recovery units, a group of receiver units, and a group of transmitter units. 4 hp f-ly. 9 il.

Description

(L

WITH

The invention relates to computing and can be used dp connect remote peripheral devices (PFCs) to the channels of computing systems.

The purpose of the invention is to increase the speed of establishing communication between the computer channels and the PFC.

In: 1 shows a functional diagram of the device; figure 2 - diagram of blocks of transceivers and multiplexer; FIG. 3 is a block diagram of requests; Fig. 4 is a diagram of the information transmission control unit; Fig. 5 is a diagram of the poll control block; Fig. 6 is a diagram of the shift register unit and the information storage unit; Fig. 7 is a block diagram of a clock recovery signal and an alternator marker; on Fig - timing diagram of the device when transmitting information from the channel to the PFC; figure 9 - the same, when receiving information from the PFC.

The device (Fig. 1) contains a transceiver unit 1, a request unit 2, an information transmission control unit 3, a polling control unit 4, a shift register unit 5, a group of transmitter blocks 6, a group of receiver blocks 7, a group of clock recovery blocks 8, a group of blocks 9 in the allocation of the marker, a group of blocks of information storage 10 and a multiplexer 11.

FIG. also indicated a group of inputs and outputs 12 of block 1, a group of inputs 13 of block 1, a group of outputs 14

SP

;about

four

ate

block), a group of inputs 15 of block 2, a hall of requests, a first group of inputs 16 of block 5 of shift registers, a group of inputs 17 of block 4 of polling control, an output 18 of the signal of the presence of a query block 2 requests, a second group of inputs 19 of polling signals of block 5 of shift registers the control signal of the parallel recording of the block 5 shift registers, the input 21 of the syncro: signal of the block 5 shift registers, I input 22 of the clocking of Manchester block; ka 5 shift registers, outputs

The polling control box 4 (FIG. 5) is designed to generate polling signals included in group 2 of outputs 19, according to signals from input group J7 and depending on the presence and priority of signals at inputs 32, -, 32 PFC requests and contains a group of nodes 62 polling controls, each of which contains the elements NOT 63 and 64, the elements AND 65-67, the elements OR 68 and 69, the element OR-NOT 70, the trigger 71, the element AND-NOT 72 and the inputs 73-75.

Block 5 shift registers (6)

i, r N / r shift registers,, 5 is designed for transform; an; ;; and: outputs 24 blocks 6 transmitters, input, formations arriving at flows 25 and outputs 26 blocks 7 receiver .-. log in

cov, outputs 27 and 28 of clock recovery unit 8, outputs;

20

: 29 blocks 8 of clock signal recovery, outputs 30 and 31 of marker emitter blocks 9, outputs 32 blocks of 10: information storage, output groups; 38 information storage units 10.

Dynes 16 and 19 of block 5, from a parallel code to a serial Minnester code at the outputs 23 of block 5 and contains a shift register 76, the number of bits of which corresponds to the number of inputs in the group of inputs 16 of block 5, a group of four-bit shift registers 77, a group of elements .

„, - j cinnyujo //, group element

Opok 1 transceivers (figure 2) 25 EXECUTIVE OR 78 and the element HF 7P

LYMACH iyaty gtggst -rt-Tf.-r .L / 7

I is intended to amplify the signals I coming from the output and output groups; 12, and to match the control time signals with the information and I contains a group of amplifier / receiver 34 signals from the channel, a group of amplifier / transmitter 35 signals from the PFC, a group of delay elements 36 control signals from the PFC.

Transmitter unit 6 is designed to convert an electrical signal input to unit 23 into an optical signal at output 30 24 of unit 6 and, for example, may contain an optical transmitter such as MTD-1.

The receiver unit 7 is prednazaichi to convert the optical signal "" / ochala received at the input 25 of the block

, Block. 2 requests (fig. 3) prednaz- 7 from the optical line, in electrical; 1G ° G ™ informational system; on the transceiver; Ca to transmit information via optical - - - "

| line at the output of 1 8 block 2 when the state of one of the control inputs from the group of control inputs 15 is changed - 40 signals from the channel of block 2 and contains a group of triggers 37, a group of triggers 38, a group of elements HE 39 , the number of elements in each of which corresponds to the number of inputs: 45 terminals and 29 blocks 8 in the form ;; groups of inputs 15 of block 2, in addition, the tional signal arriving at D s;

elements and np ° “6 blocks 8 and contains elements AND-NOT 43 and 44, two 80-83 one-vibrations, trigger 84, elements 85 and ... mountain 45 and 46, and element IPI-NE 47. 86 delays and elements; APPEARANCE

Block 3 transmission control information OR 87.

The machine (FIG. 4) is designed to form a marker (9) for highlighting a marker (FIG. 7) at the outputs 20-22 of the 3 signal unit.

transmission control information: no. on the optical line when it appears

I iiv, iojlc: iltlM v v .. jriiaiuiu, cjM net U lUpUM INPUT LO OLOX

in input 18 of block 3 of signal 18, request-counting received from optical n contains triggers 48-53, a generator of a line of information bits of the following .54 pulses, AND-NOT elements 55 and 56, NOT 57, element AND 58 and elements 59- 61 delays.

26 block 7 and, for example, may contain a serial optical receiver type MPR-1.

Block 8 recovery clock with, .g; The signal (FIG. 7) is designed to recover the clock signal at the output 27 of block 8 and to form delayed, information signals

It is designed to detect a marker in the delayed information signal received at the second input 28 of the block.

behind the marker, synchronously with the restored clock signal at input 27 -.i. unit 9, as well as for generating the signal control unit 4 of the polling control (figure 5), is designed to generate polling signals belonging to output group 19, according to signals from input group J7 and, depending on the presence and priority of signals at inputs 32, -, 32 PFC requests and contains a group of polling control nodes 62, each of which contains NOT elements 63 and 64, elements AND 65-67, elements OR 68 and 69, element OR-NOT 70, trigger 71, element AND-NOT 72 and inputs 73- 75

Block 5 shift registers (6)

intended for conversion; an; ;; and: formations entering the island

intended for conversion; an; ;; and: formations entering the island

Dynes 16 and 19 of block 5, from a parallel code to a serial Minnester code at the outputs 23 of block 5 and contains a shift register 76, the number of bits of which corresponds to the number of inputs in the group of inputs 16 of block 5, a group of four-bit shift registers 77, a group of elements .

- j cinnyujo //, group element

SUPPORTING OR 78 and the element HF 7P

cue informational information; cash on viso - - - "

alarms 28 and 29 of block 8 in the form ;; the national signal coming in on D s;

26 block 7 and, for example, may contain a serial optical receiver type MPR-1.

Block 8 recovery clock with, .g; The signal (FIG. 7) is designed to recover the clock signal at the output 27 of block 8 and to form delayed, information signals

 Consumer-9 highlighter marker (Fig.7) vw.

.. jriiaiuiu, cjM net U lUpUM INPUT LO OLOX

counting information bits received from an optical line, the following

It is designed to detect a marker in the delayed information signal received at the second input 28 of the block.

counting information bits received from an optical line, the following

behind the marker, synchronously with the restored clock signal at input 27 -.i. block 9, as well as to generate the signal 51594551

catch on outputs 30 and 31 of block 9, controlling the operation of block 10 of information storage, and contains one-oscillators 88 and 89, elements OR-NOT 90 and 91, elements HE 92-95, triggers 96 and 97, element 98 delay, element AND-NOT 99 and counter 100.

Block 10 of information storage. . (FIG. 6) is intended to receive information received at input 29 of blog 10 10 synchronously with the signal at input 31 of block 10, and store it at a signal at input 30 of block 10, and contains a shift register 10.1 and a buffer register 102.

Multiplexer 11 (FIG. 2) is intended to be formed from groups,. inputs 33 of block 11 of one group of outputs 13 and contains an element AND 103 and a group of elements OR 104, the number of which is one less than the number of inputs in each group of inputs 33 of block 11.

In Fig. 1, the optical lines 105 of the PFC interface 106 with optical lines for communication with the channel, the groups of inputs and outputs of which are connected to the inputs and outputs of the PFC 107, and the channel 108 of the computer are also indicated.

The device works as follows.

The input-output channel is connected to a group of input-output devices 12, inputs of optical transmission lines from a channel to a PFC are connected to outputs 24 of a device, and inputs of optical transmission lines of information from a PFC to a channel are connected to inputs of 25 devices. When the device is turned on, all blocks and nodes are reset to the initial zero state. The reset lines are not shown to facilitate the description of the principles of operation of the device.

When the state of one of the control buses of the channel changes, block 2 requests at output 18 generates a signal for the presence of a request to transmit information. Optical lines through which the same information string, which is a marker, followed by a chain of information bits in the Manchester serial code, goes to the inputs of all optical lines connected to 24 probes, and the number of bits of information in the chain corresponds to the number of interface buses from the channel.

Q

and

20

25

30 l

with to

40 in

45 N

50 o

55

Upon receipt of the information spreading from the PFC at the optical input 25 of the corresponding receiver unit 7, the latter converts the optical signal into Manchester’s digital information signal, from which, in the recovery clock unit 8, the output signal 29 is generated

Q delayed information signal, which is consistent (bit by bit) recording the received information in the shift register 101. block 10 information storage, and

and also the start of the counter 100 received bits in the block 9 of the marker, the information being loaded into the shift register 10J only after the marker is detected by the block 9 of the selection 20 or marker. After the required number of bits is loaded into shift register 101, the signal generated by block 9, at output 30, information from shift register 101

25 is gated to the buffer register 102, wherefrom through multiplexer 11 it enters block 1, where the necessary signal matching and amplification is performed to interact with the I / O channel according to the EC interface of the computer.

Consider polling signal generation for transmission to optical lines. The initial state of the trigger 71

, from each polling control unit 62, polling control unit 4 (FIG. 5) is zero. If the interrogation signal occurs at block 75 in the initial sample sequence, then

0 inputs 73 and 84 of the block, address identification and channel operation signals are present, it passes through AND 66 elements to the outputs of each node 62 and is transmitted to all optical institutes at the same time.

If at one of the inputs 32 requests from the PFC of the unit 62 of the polling control unit appears a single signal and the channel p responds to it sends a signal

0 polling arriving at input 75 of polling control unit 4, unit potentials are set at all inputs of element And 67 of the corresponding node, as a result of which, at the input of 1 trigger 71, a potential of zero appears5

it is in a single state, and a single potential appears at the input of the installation in O. Unit

 1594551

the potential from the direct output of the trigger 71 is fed to the input element And 65,. . because the trigger 71 of the previous node, like all the others, for the exception.

If the component under consideration is in the zero state, then at the output of the element: And 65, a single sequence is formed; Tentsnal, which through the element OR 68 I gives permission for the passage of I poll 75 at the output of the element And 66; corresponding node. In this way ; a polling signal appears at the output; that polling control node 62, on; an input 32 of which received a request from: the PFC, and is transmitted with a single signal; to the optical line connected to i of the PFC that the request came from. : In all ocTajibHHe optical lines sig;

; The polling cash is transmitted as zero. : If requests are received from several: KFK PFCs, the polling signal is sent

to the optical line that is connected to the PFC, the request from which: is of higher priority. The priority is provided by the connection of the inverted output of the trigger 71 of the subsequent.-L i node 62 of the polling control with the input; element AND 67 of the previous node. For the time being: the trigger 71 of the subsequent node does not reset to the zero state; a similar trigger will not be set before; go node. Thus, the lowest priority is given to the request 32 from the PFC, which arrived at the input of the first polling control node 62 ... After processing the block of priority requests, the processing of lower priority ones occurs.

If, when sending a polling signal in the initial sampling sequence, none of the connected PFCs 107 recognized its address, then at the output of the AND element of multiplexer 11 a single reverse signal appears, coming into the channel through block 1.

If one of the PFCs has recognized the address, then one of the inputs of the And 103 element of the multiplexer 11 receives a return sampling signal lie, as a result of which the output of the And 103 element does not generate a reverse polling signal to the channel.

Consider the operation of the device when the channel 108 input-output initiates the transfer of information to the PFC. The signals from the channel are amplified by a group of amplifier receivers 34 of block 1. When the state 8 changes

none of the control signals from the channel from the group of inputs 15 of block 2 (FIG. 3) is set to one state its corresponding trigger 37 or 38, responding respectively to the leading or falling edge of the signal, while at the outputs of the elements AND-NOT 43 or 44, a single signal appears, the leading edge of which is formed using a feedback circuit on the HE elements 41 and 42. This signal triggers one of the single vibrators 45 or 46, the output of which produces a positive pulse, with the result that outlet 18 b Approximately 2 requests appear to have a zero signal for the request to transmit information via optical lines (Fig. 8, line 2). The pulse intensity at the outputs of one-shot is set equal to three clock periods, at the same time it does not have to be less than the stabilization time. information on data buses and control buses, which for the EC interface of the computer is not less than 100.

According to the signal of the presence of a request for VK: course 18, arriving at the synchronous input of the flip-flop 48 of the transmission control block 3 (Fig. 4), the flip-flop 48 is set to one state. On the leading edge of the clock pulse following the installation of trigger one in a single state, a trigger 49 is set in one state permitting the formation of a marker. The clock pulses (Fig. 9, line 1) are output by a signal generator 54. The trigger 49 is in the single state one period of the clock signal 1 (Fig. 8, line 3), since according to the next clock signal it is reset to the zero state at the input of the installation in O. The signal from the output of the And element 56 (Fig. 8, lx-, or 5), to the input of which a sip-nap from the direct output of trigger 44 and a clock signal inverted and delayed on the IS-NE element 55 (Fig. 8, line 4), is triggered, the trigger 51 is set to the one state. The potential of logical zero, which appeared at the inverse output of the trigger 51, prohibits the execution of the Manchester clock signal at the output 22 of the information transfer control unit 3. Signal from the inverse output: /

the trigger 51 is shown by line 6 (Fig. 8); the Manchester clock signal at the output 22 of the information transfer control unit 3 is shown by line 8 (Fig. 8).

The signal at output 20 of block 3 from the inverted output of trigger 49 for the formation of a marker (Fig. 8, line 9) arriving at the control inputs of parallel recording of all the shift registers of the shift registers block 5 is loaded in parallel to all bits of all the registers of the block .. The loading and shifting of information occurs synchronously with the clock signal of the shift register (Fig. 8, line 7).

The delay element 60 of the block 3 of the transmission of information is entered to compensate for the delay on the element 58 and trigger 51, the element 59 of the delay of block 3 equalizes the delay caused by the element 60 of the delay.

The data register and control buses from the channel are loaded into the shift register 76 of the block 5 of the shift registers, except for the interrogation buses, which are loaded into the higher bits of the four-bit ones. . shift registers 77. In the lower pa3 rows of shift registers 77, three bits of the marker are loaded. The highest bit of the marker is supplied to the shift registers 77 by the potential of the logical unit formed at the output of the HE 79. Two lower bits of the marker are formed by connecting the two lower bits of the shift re-. gistrov 77 to the bus

The information obtained by shifting the low-order output of each register 77 is shown (Figure 8, line 10). .Information in the Manchester code, arriving at the outputs 23, - 23 of the block 6 of the shift registers of the outputs of the elements EXCLUSIVE ШШ 78, is shown by line 11 (Fig. 8).

When coding in the Manchester code, the logical unit is represented by the transition from the state of a logical one to the state of a logical zero, which falls at the middle of the clock period, the logical zero is represented. It is a positive transition from a state of logical zero to a state. logical unit, which comes in the middle of the clock period. The first and second bits of the marker come from the moves of the elements EXCLUSIVE OR 78

0

five

s

0

j

five

0

five

0

five

the levels of the logical unit; the third bit of the marker, the unit n of the Manchester code. In order for the period from the logical unit to logical zero, representing the unit in the Manchester code, to fall on the signal of the Manchester clock of the logical unit to the logical zero (Fig. 8, line 8), the delay of this signal is introduced to the delay element 61 of the control unit 3 transfer of information. Behind the marker, information bits are formed in the Manchester code. The information input of the sequential write of the shift register 76 is connected to the Earth potential, therefore after shifting all the information bits stored in the shift registers 76 and 77, the zeros are shifted in the latter. Thus, in the intervals between the information: ZIONN14I and parcels, zeros in the Manchester code are transmitted to the optical lines.

Consider the operation of the device when receiving information from the PFC.

A signal is fed from the optical line to the input 25 of the receiver unit 7, which is converted from the optical to a digital signal of Manchester at the output 26 of the unit 7 (FIG. 9, line 1). Line 2 (FIG. 9) represents the signals at the output of the EXCLUSIVE OR 87 element of the clock recovery unit 8. Each pulse has a duration equal to the delays on the elements HE 80 and 81 of block 8, and is formed at each transition of the Manchester signal. The pulses from the output of the EXCLUSIVE OR 87 element are received by the synchronous input of the trigger 84, which is set to one state only by pulses that exit from the element 87 in the middle of each clock cycle. This trigger mode 84 is provided by a delay element 85 included in the trigger reset circuit, which allows the trigger to remain in the zero state until the middle of the next clock cycle.

The Manchester unit in the marker is used to ensure that the first pulse arriving at the synchronous input of the trigger 84 is formed in the middle of the Manchester signal's bit period. The signal from the direct output of the trigger 84 is a recovered clock (FIG. 9, line 3).

The recovered clock signal is fed to the input 27 of block 9 of the allocated-g.

nk marker where the counter starts

100 accepted bits. The latter can only be started after the input to the installation of the O counter for video from a single potential after the detection of the marker. In order to detect the marker in the Manchester delayed signal, which is fed to the input 28 of block 9 (line 4), two one-shot 88 and 89 with recurrent restart are triggered, respectively, on the leading and falling edges of this signal.

The duration of both single vibrators is set so that all signals, except for the marker, keep the element OR NOT 90 of block 9 in the zero state. In the case of the arrival of the marker, both single-shot idle for some time, as a result of which a single signal appears at the output of the element OR-NOT 90 (Fig. 9, line 5). On this signal, both flip-flops 96 and 97 of block 9 are set to one, as a result of which a single signal is set to the inputs of the installation in O of the counter 100 of the received bits, allowing the counter to start. Trigger 96 is reset by a chain. feedback on the elements HE 92 and element 98 delay dp, in case of the arrival of the next marker, reset the 100-bit counter, which counts the number of bits in the information packet plus one for the last bit of the marker in the Manchester code,

After the recovery marker is detected, the updated clock signal at the input 27 of the marker detection unit is passed from the output of the HE element 94 to the output 31 of block 9, from where, as a shift register clock signal, it goes to the synchronous input of the information storage shift register 101 (FIG. 9, line 6 ). On the leading edge of this signal in the shift register

101nosit Manchester delayed information signal arriving at the information input of the sequential write shift register

101 (FIG. 9, line 7). After the information parcel is received completely, the output of the counter 100 of block 9 establishes a single signal, which, through the feedback circuit, resets the trigger 97 of block 9, generates a zero signal at the output of the OR-NOT 91 element and resets the counter 100 of block 9. As a result At the output 30 of block 9, a zero signal is generated (Fig. 9, line 8), on the leading edge of which the information from the shift register 101 is copied from to the buffer register 102 (Fig. 9, line 9). From the outputs of the buffer register, information goes through multiplexer 11 to the inputs of block 1, where the necessary temporal correlations on delay elements 36 are made, and the signals from the PFC that are amplified through transmitting amplifiers 35 arrive at the inputs of the I / O channel.

Consider connecting a device to an optical line m. ,,

Inputs 25 and outputs 24 of the proposed device are connected to optical lines 105, which can be used, for example, serially; manufactured optical cable type OLPG-50.

The PFC 107 is connected to the optical lines 105 via the PFC interface devices 106 with optical lines for communication with the channel: containing information receiving units and information transmitting units.

The transmission unit of information on the change of the control signal from the PFC generates a request to transmit information to the input of the optical line 105, through which the information package, which is a marker, followed by a string of information bits in the Manchester serial code enters the optical line 105 to transmit to channel.

The receiving unit receives information. information..from channel 108 from the output of optical line 105, converts it from optical to digital signal of Manchester, sequentially inserts the received information into the shift register after detecting the marker, loads the received information into the buffer, from where it comes through the necessary time delays; to the inputs of the PFC.

The application of the proposed device will allow increasing the number of connected groups of remote PFCs and increasing the speed of establishing a channel connection with a PFC due to simultaneous sprinkling of the interrogation signal into all connected optical lines.

Claims (4)

1. A device for interfacing a computer with peripheral devices, comprising a transceiver unit, a unit; information transmission controllers, a group of information storage units, a group of clock recovery units, a group of transmitter units, a group of receiver units, the group of information inputs and outputs of the transceiver unit constitute a group of device inputs and outputs for connecting to a group of information and command inputs-outputs of a computer, the information outputs of the group of transmitters of the group and the inputs of the blocks of the receivers of the groups form groups of outputs and inputs of the device for connection respectively to the information input The outputs and peripheral devices, wherein the information outputs of the receiver units of the group are connected to the information inputs of the clock recovery units of the group, the information codes of which are connected to the information inputs of the information storage units of the group, characterized in that, to increase the speed, the forming unit is inserted into the device transfer request, polling control unit, multiplexer, shift register unit, marker allocation unit group, with group of information outputs b The transceiver's locale is connected to the first group of inputs of the logical condition of the polling control unit, with the group of inputs of the request block / Q to form a request for transmission, with the first group of information inputs of the block of shift registers, the group of information outputs of which are connected to the group information inputs of a multiplexer, a group of information outputs of which is connected to a group of information inputs a block of transceivers, recording inputs and synchronous inputs storing locks Inf tion group are connected respectively to the first and second clock vyho E units vscheleni marker group and counting the clock inputs of which are connected respectively with the first and second sinhrovyhrdami .blokov Formation of clock signal group 2. The device according to Claim 1, about tl, which means that the polling control unit contains a group of polling control nodes, and the first, second and third inputs of the logical condition of the polling control nodes of the group form the first group of the logical block condition, the fourth inputs of the logical condition; the polling control group forms the second group of inputs of the logical condition block; the first outputs of the group control control nodes form a group of block outputs; the second output of the polling control i-ro node is connected to the fifth input of the logical condition (i + l) - ro the polling control node, the third output of the polling control node i-ro is connected to the sixth logical condition input (i + l) -ro of the polling control node and the seventh logical condition input (il) -ro of the polling control node, fourth output of the i-ro the polling control node is connected to the eighth input of the logic condition (il) -ro of the polling control node, each polling control node contains a trigger, three 20 25 thirty 35 The information inputs of the block 45 of the element And, the three elements of OR, the two transmitters of the group, the output of the presence, the request for the block forming the request for transmission are connected to the clock input of the transmission control information block, the first, second and third outputs of which are connected respectively with the input of the record, with the synchronous input and the clock input of the shift block. per rricTpoB, the second group of information, whose inputs are connected to the input group of the polling control unit, the second group of inputs of the logical condition of which is connected to infor. storage exits of storage units element is NOT, the element is NOT, when this is the input of the first element is NOT, the first is in the first element and is the first and second inputs of the logical condition of the node, the input of the second element is NOT connected to the first inputs of the first element OR, the second element AND and is the third input of the logical condition of the node, the second input of the first element AND is the fourth input of the logical condition of the node, the first input of the second element OR, the first input of the third element, the third input of the first element AND and p ten 15 ; , o- / Qa and594551. group information, information output groups of which are connected to multiplexer information input groups, information output groups of which are connected to a group of information inputs of a transceiver unit, recording inputs and synchronous inputs of information storage units of a group, respectively; with the first and second clock outputs of the group marker section, counting inputs and the synchronous inputs of which are connected respectively with the first and second synchronization blocks of the clock recovery signal of the group. 2. The device according to claim 1, about tl and -. I that the polling control unit contains a group of polling control nodes, and the first, second and third inputs of the logical group of polling control nodes form the first group of inputs of the logical block condition, the fourth inputs of the logical group polling control group form the second group of logical condition inputs the unit, the first outputs of the polling control nodes of the group form a group of outputs of the block, while the second output of the i-ro polling control node is connected to the fifth input of the logic condition (i + l) -ro of the control node By polling, the third output of an i-ro polling control node is connected to the sixth input of a logical condition (i + l) -ro polling control node and to the seventh input of a logical condition (il) -ro polling control node, the fourth output of i-ro polling control node connected to the eighth input of the logical condition (il) -ro of the polling control node, each polling control node contains a trigger, three 20 25 thirty 35 / element AND, three elements OR, two the NOT element, the NAND element, while the input of the first element is NOT, the first input of the first element AND is the first and second inputs of the logical condition of the node, the input of the second element is NOT connected to the first inputs of the first OR element, the second AND element - the third input of the logical condition of the node, the second input of the first element AND is the fourth input of the logical condition of the node, the first input of the second element OR, the first input of the third element AND, the third input of the first element AND and lane 1  The third input of the OR element is the fifth, sixth, seventh and eighth, respectively, inputs of the logical condition of the node, the output of the second element AND is the first output of the node, the output of the third element OR is connected to the second input of the second element OR and is the second output: node, the zero output of the trigger is e;; with the third output of the node, the unit | output of the trigger is connected to the second | inputs of the third elements AND and OR | AND is the fourth output of the node. the course of which is connected to the zero inputs of the first, third and second triggers, the information input next to it is connected to the single output of the first trigger, the information input of which is connected to the output element NOT and to the information input a sixth trigger, the single output of which is connected to the fourth input of the fourth trigger whose single output is connected to the information input of the fifth trigger, the zero output of the sixth trigger is connected to the second At each control node, the output of the first element is NAND, the output 20 25 thirty Som output of the first element is NOT connected to the fourth input of the first element AND, the output of which is connected to the first input of the NAND element and to the second input of the first element OR, the output of which is connected to the zero input of the trigger, the input of which is | which is connected to the output of the element g,, ,, AND-NOT, the second input of which is connected to the output of the second element NOT, the output of the third element AND is connected to the third j | gy input of the second element OR, the output of which is connected to the second (input of the second element AND I 3. A device according to claim 1, characterized in that the information transmission control unit contains a pulse generator, six triggers, Element I, two AND-NOT elements, U element, three elements are delayed, and the synchronous input of the first trigger is a clock input of the block , the output of the first delay element, the output of the second delay element connected to the first input - the first NAND element, and the output of the third delay element are the first, second and third outputs of the block, respectively, and in the transmission control block information and 1 output generator xs pulses are not connected with the synchronous inputs of the second and third triggers, with the first and second inputs of the second NAND element, the output of which is connected to the first input of the Hj element with the input of the second element 35 40 50 which is connected to the input of the third delay element, the zero output of the second trigger is connected to the input of the first delay element, the input element is NOT connected to the zero potential bus of the device. 4. The device according to claim 1, characterized in that the marker selection block contains two triggers, a counter, two single vibrators, two OR-NOT elements, an AND-NOT element, four NOT elements, a delay element, and the trigger input of the first single vibrator is connected to the start input of the second one-shot is the block synchronous input, the counting counter input is connected to the first input of the NAND element and is the counting input of the block, the output of the first element is NOT connected to the zero input of the first trigger and is the first clock output of the block, the output of the second element is NOT ow At the same time, the outputs of the first and second one-oscillators are connected respectively to the first and second inputs of the first OR-NOT element, the output of which is connected to; synchronous inputs of the second and first triggers, zero output of the last one is connected to the first input of the second element OR NOT, the second input of which is connected to the single output of the second trigger and to the input of the third element NOT, the output of which is connected to the input of the delay element dinene with zero input of the second trigger, whose information input is connected to the output of the fourth element NOT and to the information input delays, with sync fourth and the fifth trigger, the zero output of the last connected to the zero inputs of the fourth, fifth, and sixth triggers, the synchronous input of the latter is connected with the output of the element I, the second input of the co-first trigger, the unit output of the mountain is connected to the single output of the second trigger and to the information input of the third trigger, zero output4. The device according to claim 1, differs in that the block in the lazy marker contains two trigger counter , two one-shot, two copes OR-NOT, an element of IS-NOT, four elements of NOT, a delay element, more than the start input of the first one-vibration is connected to the start input of the second one-vibration and is a synchronized block, the counting input of the counter is connected to the first input of the element AND-NOT and is countable The input of the block, the output of the first element NOT connected to the zero input of the first trigger is the first clock output of the block, the output of the second element is NOT the second clock output of the block and the marker of the first and second one-oscillation are connected to the ne and the second inputs in the block. the first element OR NOT, the output of which is connected to the synchronous inputs of the second and first terminals, the zero output of the last one is connected to the first input of the second element OR, the second input of which is connected to the single output of the second trigger and the third input rd ale NO, the output of which is connected to WMOs delay element, the output of the connections with a zero input of the second ger, kotorog data input connected to the output of the fourth of the element HE and an information input which is connected to the second input of the element NAND, the output of which is connected to the input of the second element NOT, sixteen the stroke of which is connected to the zero inputs of the first, third and second triggers, the information input of the latter is connected to the single output of the first trigger, whose information input is connected to the output of the NOT element and to the information input of the sixth trigger, the single output of which is connected to the information input of the fourth trigger, a single output which is connected to the information input of the fifth trigger, the zero output of the sixth trigger is connected to the second the input of the first element is NOT the output 0 five 0 s five 0 0 first trigger, single output which is connected to the input of the third delay element, the zero output of the second trigger is connected to the input of the first delay element, the input element; This is NOT connected to the device zero potential bus. 4. The device according to claim 1, characterized in that the block is issued: -. The lazy marker contains two triggers, a counter, two single-vibrators, two OR-NOT elements, an AND-NOT element, four NOT elements, a delay element, the start input of the first single vibrator is connected to the start input of the second one-shot and the synchronous input of the block, the counting input of the counter is connected the first input of the element is NOT and is the counting input of the block, the output of the first element is NOT connected to the zero input of the first trigger and is the first clock output of the block, the output of the second element is NOT the second clock output of the block, while lock marker.; s the outputs of the first and second single vibrators are connected respectively to the first and second inputs of the first OR-NOT element whose output is connected to; sync inputs of the second and first triggers, the zero output of the latter is connected to the first input of the second element OR NOT, the second input of which is connected to the single output of the second trigger and to the input of the third element NOT whose output is connected to the input of the delay element whose output is connected to zero input the second trigger, whose information input is connected to the output of the fourth element NOT and to the information input first trigger, single output which is connected to the second input of the element NAND, the output of which is connected to the input of the second element NOT, you-i 17 the stroke of the second element Ш1И-NOT is connected to the installation input of the counter, the overflow output of which is connected to the input of the first element NOT, the input of the fourth element is NOT connected to the zero potential bus of the device, h, H-Device according to claim 1, characterized in that the clock recovery block contains a trigger, an EXCLUSIVE OR element, a NO HE element, two hold elements, and the input of the first element is NOT connected to the first input of the EXCLUSIVE OR element and is informational the input of the block, the output of the first delay element is the information output of the block, the single output of the trigger is the first sync. 15 32; g fet LU H I129 n, 20 94551 block output 15 The output of the second element is NOT connected to the input of the first delay element and is the second synchronized output of the block, while the input of the second element is NOT connected to the output of the first element NOT and to the input of the third element NOT whose output is connected to the second input in the clock recovery unit. -,. EXCLUSIVE OR, the output of which is connected to the trigger synchronous input, the zero output of which is connected to the input of the second delay element, the output of which is connected to the zero input of the trigger, whose information input is connected to the output of the fourth NO element, whose input is connected to the device zero potential bus. 3 J 35 "E55 I .2J w rO39 I one/ I / j  Jj 15 four “7. W " 42 18 & l D -1 C5f I " l GP CH1L 55 & l ya FIG 4 F2; fZ2 nineteen L .. 6 77 jR one  1bit FIG. eight  PPP 2 ShTG1G1 zg-1 g-1 p Fi & 9 edaktor A.Mot'sh Compiled by S. Pestmal Tehred M. Didyk Proofreader T. Malets Order 2831 Circulation 569 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 P1Eyyuzhnobystvenno-publishing combine Patent, Uzhgorod, st. Gagarin, 101 l- CDCXDC I-llllgg and  / yoos eL Subscription