SU1594485A1 - Pulsed regulator - Google Patents

Abstract

The invention relates to pulsed automatic control means and can be used as a controller in automatic control systems for compressor stations. The aim of the invention is to improve the accuracy and speed of regulation. The pulse controller contains a sensor 1, an error meter 2, the first element FROM, the first power amplifier 4, the actuator 5, the second element AND 6, the second power amplifier 7, the first integrator 8, the comparator 9, the setting unit 10, the first key 11, the adder 12 , second integrator 13, relay element 14, rectifier 15, Schmitt trigger 16, differentiator 17, first element NOT 18, element EXCLUSIVE OR 19, second element NOT 20, second key 21, inverter 22, third element NOT 23 and a constant source voltage 24. The essence of the invention is to introduce and smoothly varying in frequency and duration of the control pulses as a function of the magnitude of the control error signal. 2 Il.

Description

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The invention relates to pulsed means of automatic control and can be used as a controller in automatic control systems of compressor stations.

The aim of the invention is to improve the accuracy and speed of regulation,

Fig. 4, 1 shows a block diagram of a pulse generator; in fig. 2 - timing charts of the signals at the output of the blocks of the pulse regulator.

The pulse controller (Fig.) Contains a sensor I, a mismatch meter 2, the first element I 3, the first power amplifier 4, the actuator 5, the second element I 6, the second power amplifier 7, the first integrator 8. comparator 9. sensor 10, first key 11, adder 12, second. integrator 13, rbshshly element 14, rectifier 15, Schmitt trigger 16, differentiator 17, first element NOT 18, element EXCLUSIVE OR 19, second element NOT 20, second key 21 , inverter 22, the third element is NOT 23, constant voltage source 24.

Pulse regulator operates as follows.

The signal from sensor 1 is fed to the input of the error meter 2, where it is compared with the signal of setting 1F1 (FIG. 2, curve 30). The error signal of, for example, positive polarity (FIG. 2, curve 25) through the second closed KEY 21 is fed to the second input adder 12 (curve .43), the closed state of the second key 21 and the first key 11 corresponds to the zero level of the signal at the control input, curves 42 and 41, respectively (FIG. 2), From the output of the adder

12, the signal (FIG. 2, curve 32, the time interval t (, t,) is fed to the input of the second integrator 13, the output voltage of the second integrator 13, this decreases linearly (FIG. 2, curve 33) until will become equal to the negative level (g, 2, curve 37), the Schmitt trigger 16 triggers (FIG. 2, time t,) At this time Schmmmt trigger 16 switches to state 1 (FIG 2, curve 36, Time t), At the same time, signal 1 (curve 36, time interval

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 ) is fed to the first input of the EXCLUSIVE SHS 19 cell, the second input of which also receives the logical 1 signal from the output of the relay element 14 (Fig. 2, curve 34), since its output contains a positive error signal (Fig. -2, curve 25) output meter mismatch 2.

At the output of the EXCLUSIVE OR 19 element, a logical O signal appears (FIG. 2, curve 41, time interval), and the output of the second element NOT 20 is a logical I signal (FIG. 2, time instant, curve 42). These signals, acting on the control inputs of the keys 11 and 21, switch the first 11 and second 21 keys (curves 31 and 43, respectively), with this, the first key 11 is closed, and the second key 21 is disconnected. To the first input of the adder 12 from the output of the inverter 22 through the closed first key 11 (time interval t - -t., J) an inverse error signal is transmitted (Fig. 2, curve 31), From the output of the adder (Fig 2, curve 32, interval time t, -t) the signal is fed to the input of the second integrator 13, the output of which begins to increase linearly (Fig 2, curve 33, time t, -t). The voltage at the output of the second integrator 13 grows until it becomes equal to 11 positive level (Fig. 2, curve 38) of the Schmitt trigger 16, at this point in time (Fig. 2, time t) the output signal of the Schmitt trigger 16 ( Fig. 2, curve 36) becomes equal to the logical O,

At the same time, the first input of the EXCLUSIVE OR 19 element is signaled by a logical O (Fig. 2, curve 36, time), the second input is a logical 1 signal (Fig, 2, curve 34), since the error signal is still positive POLARITY. At the output of the EXCLUSIVE ILI 19 element, the signal of logical 1 (Fig. 2, curve 41, time interval t –t 3) is received, and at the output of the second element HE 20, the signal of logical O (FIG. 2, curve 42, interval time). After this, the first 11 and second 21 keys are switched (FIG. 2, curves 31 and 43, respectively). In the interval, the first key 11 is open and the second key 21 is closed.

Next, the process is repeated in an exaggerated manner ((L 2, time interval, tj-tj). With a decrease in the error signal (fm-. 2, curve 25), the signal level at the output of the adder 12 (Fig. 2, curve 32) decreases,

which leads to a slower increase (decrease) of the voltage at the output of the second integrator 13 (FIG. 2, curve 33), and consequently, to a decrease in the frequency of the pulses at you, during the Schmitt trigger 16 (FIG. 2, curve 36),

From the output of the Schmitt trigger 16, the pulses go to differentiator 1.7, from the output of which the differentiated signal (Fig. 2, curve 39) through the first element NOT 18 (Fig. 2, curve 40) goes to the zero input of the first integrator 8. To the information input of the integrator 8 There is also a signal (Fig. 2, curve 46) from a source of constant voltage, the value of which determines the speed HapacTaifflH of voltage (Fig. 2, curve 28) at the output of the integrator 8, P, time points t ,, t ,,

t, t, when the signal at the output of the first element NOT 18 (FIG. 2, curve 40) is equal to logical O, the first integrator 8 is zeroed out, after which the signal at its output begins to increase linearly (FIG. 2, curve 28), B the time periods of the signal (Fig. 2, curve 40) are equal to logical 1, the signal from the output of the first integrator 8 is fed to the first input of the comparator 9, to the second input of which a positive polarity signal is output from the output of the rectifier 15 (fig. 2, curve 35 ). This signal is a rectified error signal. At the output of the comparator

9 pulses appear (fig 2, curve 29) whose duration and frequency depend on the magnitude of the error signal.

The pulses from the output of the comparator 9 are fed to the first 3 and second b-elements And, to the other inputs of which the signal is output from the output of the relay element 14 (Fig. 2, curve 34), and; to the first element I 3 it is fed through the third element NOT 23 (Fig. 2, curve 45). The signal at the output of the element HE is equal to the logical O during this period. The relay element 14 serves to select the control channel

(Less or More). In case of a negative signaling mismatch.

(Fig. 2, curve 25) the channel More operates - the second element AND 6, the second power amplifier 7 and the pilot mechanism 5,

In case of a negative error signal, the channel is smaller. The third element is NOT 23, the first element is AND 3, the first power is 4 and the actuator 5. In addition, the polarity of the signal at the output of the relay element changes

14 and the switching order of the first 11 and second 21 keys with unchanged signals at the outputs of other blocks.

Thus, the accuracy and speed of the controller is increased due to smoothly varying in frequency and duration of the control pulses, depending on the magnitude of the error signal.

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Claims (1)

Invention Formula A pulse controller containing a sensor, the output of which is connected to the first input of the meter mismatch. vani, the second input of which is connected to the setting device, the first and second elements I, each of which, through a corresponding power amplifier, is connected to the corresponding input of the actuator, a first key, two integrators, an adder and a constant voltage source, characterized in that In order to increase the accuracy and speed of adjustment, an inverter, Schmitt trigger, second key, burdock element, EXCLUSIVE OR element, three NOT elements, rectifier, comparator and differentiator, output will be introduced into it The error is connected to the inputs of the rectifier, the relay element, the second key and the inverter, the output of which is connected to the input of the first key, the output of which is connected to the first input of the adder, the output of which is connected in series to the second integrator and the Schmitt trigger is connected to the first input of the EXCLUSIVE element OR and the input of the differential, the output of which through the first element is NOT connected to the zero inputs of the first integrator, the output of the second key is connected to the second input of the adder, the output of the relay element f 1-11 I1 1, gg1, gz 1-1 w IP i - fi-- --t., - ,, -., j-py.-v ...... U, 30