SU1587496A1 - Parallel counter-type adder - Google Patents

Abstract

The invention relates to computing and can be used in specialized computers and digital devices of robotic control systems for adding and subtracting numbers in both the binary number system and the number system with irrational √2 bases presented in direct, inverse, and additional codes. and also for processing vector information. The aim of the invention is to expand the functionality of performing addition and subtraction of numbers in forward, inverse, and additional codes. The goal is achieved by the fact that the parallel accumulating adder containing one-bit adders 1 1 - 1 N + 2 and a group of multiplexers 8, contains a group of elements OR 9, groups of elements AND 10, 11, elements AND 12 - 14, multiplexers 16, 17 and the triggers 18, 19 characters with the corresponding connections. 2 Il.

Description

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The invention relates to computational techniques and can be used in specialized computers and digital devices of robotic tracing systems for adding and subtracting numbers in both the binary number system and in the number system with an irrational basis presented in Weak, reverse and additional codes, as well as for processing vector information.

The purpose of the invention is to expand the functionality by performing the operations of adding and subtracting numbers in forward, inverse, and additional codes.

Figure 1 presents the scheme of the parallel accumulating adder; Fig. 2 is a diagram of a one-bit adder.

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The adder (Fig. 1) contains single-digit adders, 42 inputs 2, - 2 rant p, from the number of the adder, input 3 of the read resolution of the adder, inputs 4 and 42 of the bits of the adder sign, input 5 of the adder operation type, input 6 base type of the adder, outputs 7, -R p the views of the adder, a group of multiplexers 8, a group of elements OR 9, the first and second groups of elements AND 10 and 11, the first, second and third elements And 12-14 respectively, input 15 setting the adder mode , the first and second multiplexers 16 and 17, the first and second triggers 18 and 19.

The one-bit adder 1 (FIG. 2) contains a single-bit adder transfer input 20, a one-bit adder transfer output 21, trigger 22, first and second elements AND 23 and 24, first and second adders 25 and 26 modulo two, OR element 27 , direct and inverse outputs 28 and 29 of the sum of one-digit adders, respectively. I

The parallel accumulator adder is designed to sum both binary and vector summation represented in a binary-coded positional number system with a base. In this number system, any vector X is represented as

 x, (12) -., -X.

.x, -l1

/ 24 (1)

Considering that the weights of the bits of this code are a sequence of base degrees — f .. 1-6 L, 16 2, 4,

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the even degrees of which are the weights of the bits of the binary code, the odd ones are the weights of the bits of the binary code multiplied by, then expressions (1) can be written as

., l- iJ. ri-g 1 X.-2. (2)

 ABOUT

where values take the values:

xj, x; efo,

jcfl, 3.5 ... i42, A, 6 .... n-2

The first term of formula (2) is the sum of odd code bits, and the second term is the sum of even code bits with a base,

The peculiarity is that the code with the base - (used to record the vector, the same and at the same time, the terms of expression (2) are independent of each other. This allows the addition of two vectors to the parallel and independent addition of the component parts of the vectors If there are units in the ix bits (even or odd) terms, then the transfer unit enters the (1 + 2) -th bit of the code, in contrast to the traditional binary number system, where the unit comes in (1 + 1) -th bit d.

The adder (figure 1) can operate in two modes. The first mode of adding and subtracting operands represented in the code with a base is the second mode of adding and subtracting with binary representation of the operands.

The first mode is ensured by the presence at input 6 of the signal adder Log.1, and the second mode - by the signal Log.O. .

The proposed adder can additionally perform in these modes, addition of operands in the inverse and additional codes, as well as

convert negative numbers B inverse and additional codes,

Parallel accumulating adder when adding operands with irrational base 4 in the direct code works as follows. The summation of numbers is preceded by the setting of the adder to the initial (zero) state (the setting chains to zero are not shown). Thereafter, a single signal is supplied to the inputs 5 and 6 of the adder. A zero state is set at the input 15 of the adder. The presence of a single signal at the input 6 provides for switching in the i-th bit of the transfer signal received from a single-bit (i-2) -ro-bit adder, and at input 5, the addition operation. The adder is ready to add operands in codes with an irrational basis. The first term, for example, 1 1 I 1101, which is present at the inputs 2 of the adder, with the appearance of the 1st read signal. At the input 3, is written into the triggers 22 of the one-bit adders, since the units of the addendum will be present at the outputs of the first adder 25 modulo two, and therefore and at the control inputs of the counting triggers 22. Then, the second term code, for example 01110011, goes to the inputs 2 of the adder, and from this moment begins the process of summing the even (x 111 and x 1101) and odd (y, 1110 and y 0101) bits in parallel (simultaneously) and independent about each other. In this case, at the first stage (before the arrival of a read pulse), in each one-bit adder 1, translations are formed taking into account the state of the information trigger 22 at the input 2. the corresponding bit and transfer from the (1-2) -th bit.

At the second stage, finally, in the counting triggers 22 of all bits .- the sum is formed. The i-ro operation of the adder in the add mode, with

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adder 25 modulo two at its output a potential of the KOTopbrfi Log is fed to the control input of the trigger 22. At the same time, during the first element AND 23, it forms with the potential of Log.G, which through the element OR 27, as a unit, propagates towards the old

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The current (i + 2) -ro bit. The counting pulse, which appeared at input 3, does not change the state of the trigger 22, as well, at its control input there is a Log.O. If the input i-ro one-bit adder receives signals P; Oh and at; 1 or P. 1 and y; O, then at the output of the first modulo 25 modulo two, the capacity of Log.1 is formed, which is fed to the control input of the trigger 22 and to the fifth input of the second element AND 24, Moreover, if the trigger 22 is in the unified (zero) state then, from its inverse output to the second input of the second adder 26 modulo two, the potential Log goes. G (Log.O) and at its output a potential Log.1 (Log.O) is formed, which is fed to the second input of the second element And 24

If two Log.1s coincide (do not coincide) at the input of the second element I 24 and the potential Log is formed at its output. G (Log.O) and at the output of the element OR 27 i-ro the transfer signal 1 (P; 0) and (i-2) -th digit of the adder is formed. When the counting pulse arrives at input 3, the trigger 22 i-ro the bit switches to the opposite state. If the input of the i-ro bit receives the signals P, O and y 0, then at the output of the first adder 25 modulo two a potential Log. O is formed. In this case, at the output of the element OR 27, a signal is generated

transfer P; O is in (i-2) -A bit, and trigger 22, the i-bit bit does not respond to the arrival of a counting pulse and retains its state. Review30

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in the addition mode of p-bit numbers with an irrational base iTJ, the one entering the first input of the second adder 26 modulo two proceeds as follows. If the input 2 has i-ro bits, and the transfer input i-ro of the one-bit adder 1 through the multiplexer 8 receives the transfer unit. 1 of (i-2) -ro bit, then if two signals at the input of the first match

55

con for both even and odd bits

When adding the maximum positive numbers, the units of the transfer of the (n-1) -th and n-th bits enter, respectively, the (n + 1) -th and (n + 2) -th bits.

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adder 25 modulo two at its output, a potential of Log. O, KOTopbrfi is fed to the control input of trigger 22. At the same time, at the output of the first element And 23, a potential of Log. G is formed, which through the element OR 27, as a unit, propagates to the side old l x

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The current (i + 2) -ro bit. The read pulse, which appears at input 3, does not change the state of trigger 22, since Log.O. is present at its control input. If the input i-ro one-bit adder receives signals P; Oh and at; 1 or P. 1 and y; O, then at the output of the first adder 25 modulo two, the potential of Log.1 is formed, which is fed to the control input of the trigger 22 and to the first input of the second element I 24, Moreover, if the trigger 22 is in the single (zero) state, then from its inverse output to the second input of the second adder 26 modulo two receives the potential Log. G (Log.O) and at its output a potential Log.1 (Log.O) is formed, which is fed to the second input of the second element And 24.

If two Log.1s coincide (do not coincide), the potential Log is formed at the input of the second element 24 and its output. G (Log.O) and at the output of the OR element. 27 of the i-th digit, the transfer signal 1 (P; 0) and (i-2) -th digit of the adder are generated. When a counting pulse arrives at input 3, the trigger 22 of the i-ro bit switches to the opposite state. If the input of the i-ro bit receives the signals P, O and y 0, then at the output of the first adder 25 modulo two a potential Log. O is formed. In this case, at the output of the element OR 27, a signal is generated

transfer P; O is in (i-2) -A bit, and trigger 22, the i-bit bit does not respond to the arrival of a counting pulse and retains its state. Review0

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in the addition mode of n-digit numbers with an irrational basis iTJ is single5

con for both even and odd bits

When adding the maximum positive numbers, the units of the transfer of the (n-1) -th and n-th bits enter, respectively, the (n + 1) -th and (n + 2) -th bits.

in which, as in the triggers 18 and 19 characters, before the summation, zero information is recorded. The result of the sum from the direct outputs of the flip-flops 22 through the elements AND 10, to the second inputs of which the inverse outputs of the flip-flops 18 and 19 are connected, and through the elements OR 9 enters the outputs 7 of the adder.

When adding binary operands, d (the second mode of operation), in contrast to the considered mode, the transfer unit ix of one-bit adders go to the second information inputs (i + l) -x multiplexers 8 (a g not to the first information inputs (i + 2) - x multiplexers 8). In addition, in the second mode of operation, the potential of Log.O. is applied to the input 6. The bit width of binary operands is n + l bit. The rest of the procedure of the addition operation at all stages is similar to that described.

Consider the operation of a parallel accumulating adder in subtraction mode 25 in codes with an irrational LG base. In this mode, the adder before the operation is also set to the initial state (zero state), after which a zero potential is given to input 5, and a single potential to input 6 and a single state is established at input 15. Then, n + 2 bits reduced by triggering to its inputs 2 are written to the adder trigger 22, followed by the application of a read pulse to input 3. The process of subtracting, as well as adding, occurs simultaneously, independently and equally among even and odd bits and starts at the time of application to the inputs 2 of the adder n + 2-bit subtracted. Reduced and subtracted are presented in direct codes. By 45 analogies with addition, subtraction is convenient. o be considered on the basis of the work of the i-ro bit adder.

If at the entrance to the input 2 i-ro

bit y 1, the transfer signal receives a loan from (i-2) -ro discharge, then if two signals coincide at the input of the first adder 25 j modulo two, the potential of Log.O is formed at its output, which is fed to the control input of the trigger 22. At the same time at the output of the first element And 23 form8

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Potential Log.1 is detected, which through the OR 27 element at the output of the transfer, as a unit of loan z, spreads towards the (i + 2) -ro discharge. Trigger 22; retains its state. If the input of the i-ro bit receives signals Z; O and y 1 or z; 1 „ 5, then at the output of the first adder 25; modulo two, the potential of Log. G is formed, which is fed to the control input of the trigger 22; and the first input of the second element And 24; j If the trigger is in the unit (zero) state, then from its inverse output to the second input of the second adder 26; modulo two, the potential of Log.O (Log.1) enters and at its output a potential of Log-.O (Log. I) is formed, which is fed to the second input of the second element I. If there is a mismatch (coincidence) of two LogG.G at the input of the second element I 24; at its output, a potential of Log.O (Log.1) is formed and, on the transfer bus, a loan signal z is generated; O (z; 1). At the time of arrival at the input 3 of the counting pulse trigger 22; switches to the opposite state.

When subtracting in the direct code, in the case when the deductible is less than the deductible, loans arise in the triggers

18 and 19 characters pre-set to zero state, which are distributed as multipliers in multiplexers 16 and 17.

With their help, the triggers 18 and 19 are set to one state, which means that the corresponding bits are negative. There may be cases when a unit of credit to sign triggers occurs only in odd or even even bits, then, respectively, only the trigger

The 19 characters or only the character trigger 18 is set to one state. Dp of obtaining the result of the subtraction at the outputs 7 in the direct code, since in the triggers 22 the difference of numbers is fixed in this case

X and y in the additional code, it is necessary to subtract one from the lowest odd (first) digit of the adder with negative even Hi.ix bits, or from the least significant even (second) bit with negative even digits and together from the odd even even (first and second) bits with a negative result. Due to the fact that the input 15 in the subtraction mode is in the single state, the single signals of the trigger 18 and 19 of the sign go to the first and second information multiplexers 8 of the second and first bits, respectively, in the first case through the sequentially connected elements And 12 and 14 , and in the second case, through the elements of And 13. And then the subtraction from the additional result code recorded in the triggers 22 of the unit of the even and odd bits or two units takes place. Loan for both groups of bits after a read pulse is fed to input 3.

The result of the subtraction is removed from the inverted inputs of the triggers 22, if all the bits are negative, or from the direct outputs - if all the bits are positive. In the case when one group of bits is negative, and the other is polol-effective, negative bits are taken from the inverse outputs, and positive bits are taken from the direct outputs of the trigger 22. When the binary n + 2 bit operands are subtracted, the units i- The ro bit of the adder is made into a (1 + 1) th bit, i.e. on the left is worthwhile. Dp provision of this multiplexers 8 are connected to the transfer input i-ro of the one-bit adder transfer output from the (i-l) -ro discharge.

The difference between the subtraction operation of binary operands is that both trigger 18 and 19 are always set to one (when decremented is less than subtracted) and that Log.O. is present at input 6. To obtain the result of the subtraction in the direct code, it is necessary to subtract the loan unit from the youngest category. Since at the first input of the element And 14 there is a potential of Log.O, the unit of loan from the output of the trigger 19 characters through the element 13 will propagate only for the first time of the adder. For the rest, the subtraction process is no different from what was previously discussed; Moreover, if the result of the subtraction is negative, then its direct code is removed from the inverse outputs.

1587496

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triggers 22 adders, otherwise - from the direct outputs of the same triggers.

 A parallel adder can be used to convert direct codes of negative numbers to inverse and additional codes. To obtain the inverse code of a negative number JO in terms of the irrational basis, it is necessary to set the triggers 18 and 19 of the sign to one state, and to the inputs of 2 (n + 2) bits to submit the direct code of the number, to the inputs of 15 5 and 6, the signal of the Log.G and after the response time of the adder 25 modulo two, apply a 3-pulse readout to the input 3. In this case, at the outputs 7 of the adder, the inverse 0 code of the source operand will be present. The conversion of a negative number to an additional code consists in the fact that after writing the number to the adder, it is necessary to send a zero signal to input 5, 5 and to the inputs 2 of the first and second bits (to the youngest odd and even bits) the adder has two single credits. After that, after a period of time equal to or greater than 0 the delay time of information on the first adder 25 modulo two, send a read pulse to the input 3.

Upon expiration of the loan time, an additional code of a negative number will be present at the inputs 7 of the parallel accumulating adder. In the case when odd divisions are negative and even are positive and vice versa, the trigger is set to one sign i 19, and the trigger 18 sign is set to zero and vice versa: the trigger 19 sign is set to zero The state and trigger 18 characters - in the unit. In this case, the process of obtaining the reverse code number is similar to the previously discussed. The difference is that the reverse code of positive bits is removed from the direct outputs of the flip-flops 22, and negative ones from the inverse outputs of the same flip-flops.

Dp of formation of an additional code in this case it is necessary to attach a unit of credit to the input 2 of the first or second bits of the adder depending on the state of the flip-flops 18 and 19 characters and at zero signal

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15

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at input 5, apply a read pulse to input 3. It should be noted that the additional code and a negative number can be obtained by setting input 15 to one, then with a zero signal at input 5, the output signals of the direct outputs of the flip-flops will be 18 and 19 digits, which, through the elements 12-14, respectively, arrive at the inputs of the loan of the second and first one-bit adders.

Conversion of negative binary numbers to inverse and additional codes is similar to the considered conversion. The difference is that to obtain an additional binary number code, zero potential is applied to input 6

A proposed adder can perform an addition operation with numbers represented in forward, inverse, and additional codes, both in binary representation of operands, and in number with an irrational base of -l | 2. In this case, the following variants of the operands x and y are possible, when the first addendum is represented in the forward code, and the second in the supplementary and inverse codes, when both cIiaraeMbix are positive (inverse and - the complementary codes coincide with the forward one), then this The variant is considered earlier. . If the second operand is negative, then, after writing to the triggers 22 of the first operand, the reverse or additional code of the second term is fed to the inputs of the 2 bits of the adder. In this case, for the return code, the input 15 is set to the zero state, for the additional one - to the single state. .If the negative operand is received in binary form, then two or more units of the unit with the coma and the unit of the unit can be obtained from one unit with the other.

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20

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de, then both flip-flops 18 and 19 are set to one state,

In the case when the second operand is a number with an irrational base -J2, then depending on the sign of the corresponding group of bits (even and odd), the signers trigger 18 and 19 are set to the appropriate state. In this case, the signal Log.1 must be present at the input 5, since the add-on operation is performed. Then, at input 3, a read pulse and triggers 22 are set 45

50

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This is the case, and dyuyu ni mu arg is given once d (times d din (k + w

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They are in the state corresponding to the numbers X and Y. If the second operand was specified in the reverse code, then the result of the summation in the direct code is removed for binary codes in the same way as the result of the subtraction in the direct binary codes, and for numbers with an irrational base it is similar to subtraction in direct codes with an irrational basis l | 2 When the second term is specified by an additional code, then after the installation of the flip-flops 22 in the position corresponding to the sum of the numbers X and y, it is necessary to apply the potential of Log.O (subtraction operation) to the input 5. With the addition of binary operands, the transfer unit enters through the element And 13 to the multiplexer 8 of the first bit, at the inputs 2 - Log.O. In the subtraction mode, the transfer unit is subtracted from the least significant bit. With the arrival of a new read pulse at the outputs 7, the result of summation in the forward code is obtained. For codes with irrational grounds, depending on the sign of the corresponding bit group, the transfer unit enters the corresponding lower bit, and for both negative bit groups, two transfer units are received in the second and first bit. This happens in the same way as transferring negative numbers with an irrational basis — into additional codes.

Claims (1)

Formula invented and 0 five zo 0 five 0 five Parallel accumulating adder containing n + 2 one-bit adders (n is the number of digits) and a group of multiplexers, with the inputs of the digits of the number of the adder connected to the inputs of the corresponding multiplexers of the single-bit adders which are combined and connected to the input of the task of the type of base of the adder, the input of the read permission of which is connected to the corresponding inputs of the one-bit adders from the first to (), output The transfer of the k-ro one-bit adder (k 1, ..., p) is connected to the first information input (k + 2) -rp group multiplexer and to the second information input (k + 1) th group multiplexer, transfer output (p +1) the one-bit adder is connected to the second information input of the (n + 2) -th group multiplexer, the first information input of the first group multiplexer is connected to the zero potential adder input, the input of which operation type is connected to the corresponding one-time totalizer inputs from the first by (n + 2) th, differing by that for the purpose of distributing the functional capabilities of the 1C1On capabilities by performing the operations of adding and subtracting numbers in forward, inverse, and additional codes, it contains a group of elements OR, the first and second group of elements AND, the first and third elements AND, the first and the second multiplexers, the first and second triggers of the sign, with the direct and inverse outputs of the first sign trigger connected respectively to the first inputs of even elements of the second and first groups, the direct and inverse outputs of the second sign trigger Vym odd inputs of the AND vto10 20 25 the bits of the adder, the direct outputs of the first and second sign triggers are connected respectively to the first inputs of the first and second element I, the second inputs of which are combined with the input of the assignment of the mode of the detector; the first input of the third element And, the second input and output of which are connected respectively with the output of the first element And and with the first information input of the second multiplexer group, the output of the second element And connect with the second information with the first input of the first phylectropic group, the transfer output of the (n + 1) th single-bit mattress is connected to the first information input of the second multiplexer, the output of which is connected to the information input of the second sign trigger transfer output of the (n + 2) th one-bit adder connected to the second information input of the second multiplexer and to the first and second information inputs of the first multiplex, the output of which is connected to the .uiJci, the output of which is connected to the in- formation and the first trigger output of the fVMM PGTPOOPG GTTG ,, ,,, ffii I The first outputs of the first to (n + 2) th sum of one-digit adders are connected to the second inputs of the corresponding And elements of the first and second groups, the outputs of which are connected to the first and second inputs of the corresponding RShI group elements. outputs which are outputs / 70 "l from 29 The sign of the permission inputs of the first and second sign triggers are connected to the read resolution input of the adder, the inputs of the character setting 35 are connected to the installation inputs of the corresponding sign triggers in I. 2; , ten 20 five the bits of the adder, the direct outputs of the first and second sign triggers are connected respectively to the first inputs of the first and second elements I, the second inputs of which are combined and connected to the input of the adder mode setting, the input of setting the base type of which is connected to the control inputs of the first and second multiplexers and with the first input of the third element And, the second input and output of which are respectively with the output of the first element And and with the first information input of the second group multiplexer, the output of the second element And is connected with the second information input of the first fliptic group, the transfer output of the (n + 1) -th single-digit adder is connected to the first information input of the second multiplexer, the output of which is connected to the information input of the second sign trigger of the transfer output of the (n + 2) -th one-bit adder connected to the second information input of the second multiplexer and to the first and second information inputs of the first multiplexer, the output of which is connected to .uiJci, the output of which is connected to the Formationion, m input of the first trigger .uiJci, output to torogo coupled to an Information, m Trigg first input ffii I  "L 29 the sign, the enable inputs of the first and second sign triggers are connected to the read resolution input of the adder, the inputs of the character setting bits of which are connected to the installation inputs of the corresponding sign triggers in I. 2;