SU1583967A1 - Device for presentation of information on screen of television receiver - Google Patents

Abstract

The invention relates to automation and computing and can be used in automated control systems, communication systems and computing as a device for displaying information on the screen of a television receiver. The aim of the invention is to increase the information content of the device. The device contains a master oscillator 1, a pulse distributor 2, a code converter 3, a 4-character counter, 5 television lines counter, 6-character lines counter, frequency divider 7, clock generator 8, address multiplexer 9, first decoder 10, first trigger 11, block 12 control, the first 13 and second 14 blocks of RAM, data multiplexer 15, character generator 16, second decoder 17, video signal generator 18 with corresponding connections. The introduction of the second RAM unit 14, the second decoder 17 and the frequency divider 7 made it possible to increase the information content of the device by making it possible to form pseudographic elements of full familiarity size, forming a marker from 1 to 3 TV lines wide and flickering, reversing and highlighting characters. 10 il.

Description

sd

00

oe so oe

The invention relates to automation1 and computing technology and may also be unused to automated control systems, communication systems and computing equipment as a device for outputting information to a television receiver screen.

The purpose of the invention is to increase the information content of the device.

Pa figs. 1 is a functional block diagram of the device; in fig. 2 is an electrical circuit for a character counter; in fig. 3 - electrical circuit diagram of the sync pulse generator; in fig. 4 is the electrical principle of the address multiplexer; in fig. 5 is a circuit diagram of the first decoder; in fig. 6 is an electrical circuit diagram of a control unit; Fig. 7 is a circuit diagram of a data multiplexer; pas figs. 8 is a circuit diagram of the second decoder; pas figs. 9 is a circuit diagram of a video signal driver (PCF); in fig. 10 is a diagram of the operation of the device.

A device for displaying information on the screen, a television receiver contains a master oscillator 1, a distributor 2, pulses, a converter of 3 codes, a counter of 4 characters, a counter of 5 television lines, a counter of sign lines, a frequency divider 7, a driver of 8 clock pulses, an address multiplexer 9, the first decoder 10, first trigger 11, control unit 12, first 13 and second 14 RAM blocks, data multiplexer 5, character generator-16, second decoder 17, video signal shaper 18, first address input 19 and second address the first input device 20, a control input device 21, a control input device 21, information input-output device 22, output device 23, video signal.

The 4 character counter contains the first 24 and second 25 counters, the first block 26 of the elements is NOT, the first element is NOT 27.

The sync pulse generator contains the first permanent memory unit 28 (ROM), the second element NOT 29, the first 30 and second 31 blocks of elements AND, the third element NOT 32.

The multiplexer 9 addresses contains the first 33, second 34 and third 35 multiplexers.

The first decoder 10 comprises a second permanent memory unit 36 (ROM), the fourth element is NOT 37.

Control unit 12 contains the second 3Ј | the third 39 triggers, the first element AND 40, the first element AND-NO 41, the first group of 43 elements AND-NOT, the second element AND-NO 43, the second element AND 44, the second troupe of 45 elements AND-NOT, the fifth element NOT 46, third element m 47, the second block 48 elements NOT.

Data multiplexer 15 contains the fourth 4e), powered 50, sixth 51, seventh 52, eighth 53 multiplexers, first register 54 ..

The second decoder 17 contains a decoder 55, the third block 56 of the permanent memory (ROM), the fourth element And 57, the fourth trigger 58.

The shaper 18 of the video signal contains the third element AND-NOT 59, the second register 60, the sixth element NOT 61, the third group 62 elements IS-NOT, the seventh element NOT 63, the fourth element AND-NOT 64, the keys on the transistors 65- (n load cells on resistors 69-72. The positions 72-122 denote the inputs and

the outputs of the respective units of the device.

0

The device works as follows.

In the initial state of the device, the outputs of the decoder 10 take the state corresponding to the screen regeneration cycle (mode), namely: the first output 88 is set to the zero state, in a bullet

The 5th state also includes the first, second, seventh, eighth and ninth bits of the second output 89 of the decoder 10, which is of the ninth type. The state of the third to sixth bits of the second output 89 of the decoder 10 is determined by the current scan address or the cell address of blocks 13 and 14, which store the code of the current character and character attribute, respectively. The trigger 11 is set to the zero state, n is the one state of the inverse output of the trigger connected to control unit 5. The input of the multiplexer 9, causes the connection to the address inputs of blocks 13 and 14 of the current decade address of the displayed symbol, and to the first address input 90 of the decoder 10 - the address

The Q of the selectable block in blocks 13 and 14. The start bits of the address bus in the regeneration mode always assume the zero state, since the sampling of blocks 13 and 14 is a phase change.

Zero input status 84 request

5 of the control unit 12, as well as the zero state of the seventh, eighth and ninefold bits of the control input 85, which is the nine-bit bus, leads to blocking of the data multiplexer 15, since the single state of the first

0 and the second bits of the third output 81 of the control unit 12 blocks the multiplexers 51-53 of the block 15, and the bullet state of the fifth bit of the third output 51 blocks the register 54 of the multiplexer 15. In addition, the unit state of the third bits

The second 80 and fourth 82 outputs of the control unit 12 sets the mode for reading information from the blocks 13 and 14 of the memory.

For the beginning of the formation of the raster (the next half-frame), the zero state of the line of counters of characters 4 and television lines 5 and the single state (00001) of the counter 6 character lines are taken. The clocking of the l-ikey counters is carried out from the distributor 2 pulses. The cycle of operation of the distributor 2, performed on the shift register, consists of seven cycles (seven generator oscillators 1) and determines the duration of the horizontal scanning of the symbol (Fig. 10).

In the first cycle of the operation of the distributor - 2, the backward (positive) pulse edge at the first output 73 of the distributor 2 is increased by 4 units of the counter. In this case, the second output 99 of the counter 4 signifies four lower bits, and the second output 103 of the driver 8 -j- seven high-order bits of the address bus of the eleven-digit code of the current scanning address.

Output b of the ROM 28 of the driver 8 takes the state "Log. About and through the block 30 elements And causes blocking of the formation of discharge pulses of a 4-character counter and a counter of 6 character lines at the inputs of elements And 31 of the former 8. In addition, the level "Log. O in the second discharge of the fourth output 104 of the former 8 is an indication of the formation of the active part of the line (frame), and the level Log. On the first output 101 of the imaging unit 8 corresponds to the absence of a synchronizing pulse in the composition of the full video signal.

In the second cycle of the operation of the distributor 2 pulses with a pulse of negative polarity at the output 74 of the distribution -. 1 2, the trigger 39 of the control unit 12 is set to zero.

tel tel: soy

causing the formation of a single state in the first and second bits of the outputs 80 | And 82 of the control unit 12, which are the sample resolution signals of the blocks 13 and 14 ..

level "Log. O, which is formed in the second digit of the fifth output 83 of the block 12, received at the address input 91 of the decoder 10, causes the third, fourth, fifth, and sixth bits of the second output 89 of the decoder 10 to be set to zero, corresponding to the absence of sampling resolution signals blocks 13 and 14.

The third cycle of the operation cycle of the pulse distributor 2 is idle for all: (device operation modes.

In the fourth and fifth cycles of the operation cycle of the distributor 2 pulses are negative. Noah; The polarities formed by the corresponding outputs 75 and 77 of the distributor 2 and the groups of synchronous inputs 87 of the control unit 12 that arrive at the first and second bits cause the generation of polling signals of the positive polarity of the sampling resolution signals on the AND-HI elements 42.

The outputs of the I-NC elements 42 of the control block 12 are held in one state by the zero-level sample inhibit signals on input 85.

Thus, the four clock cycles of the operation of the pulse distributor 2 (clock cycles e five) are preparatory (preset).

In the sixth cycle of the operation of the distributor 2 pulses, the leading edge of the negative polarity pulse at the sixth output 78 of the distributor 2 trig 5 ger 39 of the control unit 12 is set to one with respect to the synchronous input. Level "Log. On the inverse output of the trigger 39 of the block 12 through the element AND NOT 41 unlocks the elements AND NOT 42.

The single state of the second bit of the fifth output 83 of the control unit 12 causes the unblocking of the corresponding outputs of the RAM sampling resolution of the decoder 10.

Transition to the unit state of the third,

5 of the fourth, fifth and sixth bits of the second output of the decoder 10 is carried out in pairs: the third and fourth when selecting the first half of the blocks 13 and 14; and the fifth and sixth when choosing the second half of blocks 13 and 14.

0The unit state of these bits causes the formation of a zero state at the corresponding output of the block 42 of the NAND elements, which causes unlocking at the input of the sample resolution of the corresponding bank in blocks 13 and 14.

5 The character code stored in the selected

the cell of the block, with its Q / D outputs goes to the address inputs of the character generator .16, and the attribute code stored in the selected cell of block 14, with its Q / D outputs, goes to

Q address inputs 112 decoder 17.

 A symbol horizontal scan code is generated at the first output of character generator 16 in accordance with the input character code and the four-digit code of the current TV line. At the second output of character generator 16, a two-bit pattern is formed, which carries information about the state of the first raster point in the horizontal symbol scroll or whether there are commands — beam quenching (screen), beam activation. The signals of the illumination (formation of the white level), the resolution of the direct or inverse signals of the luminance component are formed at the outputs of the decoder 17. The seventh cycle of the operation of the pulse distributor 2 is idle.

eIn the first cycle of the distributor cycle 2

 a negative polarity pulse, which is formed at the output 73 of the distributor 2, gates the decoder 55 of the decoder 17.. at one of the outputs of which the level "Log. A. Activating the output Q1 of the decoder 55 causes the setting of the trigger 58 for screen blanking ("O at the inverse output - blanking) in one state. Activating the QO output of the decoder 55 causes a reset on the R input to the zero state of the trigger 58, corresponding to the screen exposure resolution. Activating the output Q2 of the decoder -58 causes the first raster point to be illuminated by the horizontal sweep of the symbol.

In the same first cycle of the distributor 2 pulse at the output 76 of its output, a positive signal is formed, which, in accordance with the mode input of the transducer 3, sets the latter to parallel recording mode. The next clock pulse of the master oscillator I, arriving at the synchronous input of the converter 3, makes parallel recording of the input information into the converter 3 (along the negative edge of the pulse). At the same time, at the output 73 of the distributor 2, the level "Log. 1, and on outputs1 74 and 76 - the level “Log. O. Level "Log. O, which is set at the input of the converter mode 3, puts the latter into the shift mode, and on the leading edge (negative) of the pulse at the output 74 of the pulse distributor 2, the attribute attributes are returned in the register 60 of the imager 18.

Thus, the cycle of sampling the horizontal scan code of the symbol and the code corresponding to the attribute attribute symbol is completed, and, starting with the end of the first clock cycle of the pulse distributor 2, the horizontal scanning of the symbol begins in accordance with the established attribute attribute (i.e. generation raster dot) on the screen of the television receiver.

At the same time, the counter is 4 digit long, i.e., the next cycle of sampling the sweep code and attribute code begins. The nature of the horizontal ramp of the character (the horizontal scan code in the 5X7 character matrix and in the 7X 11 pseudo-character matrix) is determined by the number of the current TV line arriving at the first group of inputs of the 16 character generator from the 5 TV lines counter.

Formed by the described method, a successor of noshypulses at the output of converter 3, which is a positive capacitive component, from the output of converter 3 enters the input of generator 18, where, depending on the attribute attributes, it is modified (inverted, blocked, MODULATED, MODIFIED)

is filled) and is mixed with the synchromesy coming from the generator unit 8. Thus, cycle by cycle, the active part of the television line is formed. Upon finalization of the formation of the last character in the television line (80th character), the output of the Q6 ROM 28 of the synchronizer 8 generator is set to the level "Log." 1, and on the remaining outputs of ROM 28 - the level “Log. ABOUT.

At the end of the last cycle of generation of the active part of the television line (80th character) in register 60 of block 18, the outputs QI and Q2 of the register are set to "Log. O and cause the blocking of the direct and inverse luminous-components of the inputs AND-NOT 62 to the inputs.

The by-passes of the AND-NE elements 62 are set to one, thereby causing the activation (setting the level “Log. 0) of the output of the AND-NE element 64, which causes the formation of the damping level at the output of the block 18.

The duration of the damping of the beam is 20 cycles of operation of the distributor 2 pulses. When the counter reaches 4 characters of the state defining the right edge of the formed raster 80-2, a cycle, a single level is formed at the output of the Q7 ROM 28 of the driver 8, causing the formation of a single level at the output of the third element 30 and accordingly at the exit 101 of the driver 8.

The unit state of the input of block 18, connected to the output of driver 8, is stored in register 60. The level "Log. 1 at the input element HE 63 of the block 18 causes the formation at the output of the block 18 of the leading edge of the horizontal sync pulse. The duration of the generated horizontal sync pulse is eight cycles of operation of the 2-pulse pulser.

At the end of the synchronization pulse, the screen continues to be quenched for another ten cycles of the distributor 2 pulses. When the counter reaches 4 characters of the state, which determines the duration of the full television line, a single level is formed at the output Q4 of the ROM 28 of the driver 8, which in turn causes the formation of a single level at the output of the Element of the 30-unit I.

In the fourth cycle of operation of the pulse distributor 2, a negative pulse at the clock input 105 of the generator 8 excites at the output of the element HE 29 a single pulse, which, through the second element of the block 31, resets the counter of 4 characters.

The vertical unfolding of the character string is eleven television lines, with the familiar character taking up seven television lines — from the second to the eighth (zero is a space), and the familiarity of the pseudo-character — all eleven. The TV strings of the sign strings, from nine to eleven, are also the field

Attributes: Dev - underscore, dec - and eleven - marker.

Upon completion of the formation of the eleventh television line, the counter of 5 TV lines of the young lines is reset, and the counter of 6 rows of lacquer lines, connected with the output of the counter 5, increases its state by 1.

This is how the formation of a vertical raster sweep occurs until the last (25-) sign is formed.

Upon completion of the formation of the 25th sign, the hey line on the output Q6 of the ROM 28 of the former 8 forms the level "Log." 1, i.e., the leading edge of the personnel extinguishing pulse. For one more sign line, the front shelf of the frame extinguishing pulse is exhausted, after which the output Q7 of the ROM 28 of the driver 8 is set to one, the caller is formed by the leading edge of the frame clock pulse at the output of block 18. The duration of the frame clock and pulse generated by the device , equal to-HJ duration of one character string. | The duration of the back shelf of the extinguishing pulse generated by the device consists of two character strings.

When the counter reaches the sign state lines corresponding to twenty-nine sign lines, the level "Log. I is formed at the output Q5 of the ROM 28 of the former 8. In the fourth cycle of operation of the distributor 2 pulses, a pulse of negative polarity is formed in the first discharge of output 104 of the driver 8, and a positive polarity in the third discharge. These pulses reset the counter of 6 character lines by the installation inputs and reset the prohibition trigger 58 (if it was installed during the screen generation) of the decoder 17.

Screen quenching (single output state Q6 of the ROM 28 of the former 8) is carried out within one null sign line. During the screen blanking time, the block 17 of the decoder 55 of the block 17 is blocked (banned) in order to prevent false switching of the trigger 58.

At the end of the zero character string nf output Q6 of the ROM 28 of the driver 8, the level "Log. O and the generation of the first television line of the next frame begins.

In the information recording mode, the device operates as follows.

 If the state of the second address input 20 of the device, which is the four most significant bits of the input address bus of the device, coincides with the address of the device stored in the ROM 36 of the decoder 10, in the second bit of the output 89 of the decoder. single signal is generated

U1 n

Aries, which in control unit 12 controls the output of the second element HE 48,

0

0

5 5

0

five

0

five

0

five

which is the output of the sample disable signal of other devices in the system.

With the arrival of the "Record" command (the level "Log. O in the first section of the device input 21), the first output 88 of the ROM 36 of the decoder 10 is activated, at which the level" Log. " 1, which is a request for access to on-screen RAM, i.e., blocks 13 or 14. This signal unlocks trigger II via the information D input and trigger 38 of the control unit 12 via the installation R input.

The state of the information input of trigger II is polled each time in the second cycle of the operation of the distributor 2 pulses with the front (negative) pulse front at the output 74 of the distributor 2 pulses. In the presence of a request signal of a single level, the trigger is transferred to the single state, and a zero level at the inverse output of the And trigger causes switching of the address multiplexer 9. Level "Log. On the control input 95 of the multiplexer 9, the address causes the output of the multiplexers 33-35 of the state "A.

In the same cycle of operation of the distributor 2 pulses, by the installation R-input, the trigger 39 of the control unit 12 is set to the zero state, the unit state of the inverse output of which, together with the single output state of the AND 40 element, causes the formation of the level "Log. O is at the output of the NAND 41 element. This signal prohibits sampling of blocks 13 and 14.

At one of the outputs Q2, Q3, Q4, Q5 of the ROM 36 of the decoder 10, depending on the state of the group of inputs of the decoder 10 connected to the output group of the multiplexer 9 address and two high bits of the device's twelve-bit address bus, the Log level is formed. I. Level “Log. 1 is also formed at the sixth output of the ROM 36 of the decoder 10, which is the signal for writing into RAM.

The output state of the Q7 of the ROM 36 of the decoder 10 determines the direction of information transfer in the write cycle: with a single state of the output Q7 of the ROM 36 - from the external data bus (device input 22), in block 13 at zero - from the external, data bus in block 14 .

The single state of the seventh bit of the input 85 of the control unit 12 causes, in conjunction with the single state of the input of the request 84 of the control unit 12, the setting of the "Log. About the output element AND-NOT 43.

Thus, the recording mode is set in blocks 13 and 14.

The single state of the first and seventh bits of the input .85 of the control unit 12 causes the formation of a single level

85 causes the formation of a zero level in the first or second discharge of output 81 of block 12

In the unit state of the eighth bit, the input 85 from the input - output 22 of the device is fed to the input / output (Q / D) of the unit 13 through multiplexers 51 and 52.

In the zero state of the eighth bit of the input, 85 information from the inputs-outputs of the device 22, namely from the lower four bits of the device's bi-directional data bus, is fed to the inputs-outputs. (Q / D) block 14 through multiplexer 53.

Thus, the address of the updated cell of the And or 14 blocks is preset and the data on the inputs-outputs of the RAM, i.e. the character code, pseudo-symbol written in block 13, or attribute code recorded in block 14, is preset. In the fourth cycle of the cycle distributor 2 pulses level "Log. O, in the first discharge of input 87 of control unit 12, through element I 40 and element I-NE 41 unlocks the element I-NO 12 to the second inputs and the code combination set at its inputs-outputs is written to the selected RAM cell.

E5 of the second cycle of the distributor 2 pulses on the leading edge (negative) of the pulse in the second section of the input 87 of the control unit 12, the trigger 38 is set to one and the output of the first element 48 is set to Log 0, which is a device readiness confirmation signal. .

Level "Log. 1 in the first discharge of the output 83 of the control unit 12 connected to the direct output of the flip-flop 38, received for the first digit of the input 91 of the JO decoder, causes the sample enable signal set to one to be reset at one of the bits (third to sixth) output 89 of the decoder 10, and resetting the recording resolution signal — by setting the zero offset on the seventh discharge of output 89.

Level "Log. O at the output 79 of the control unit 12 causes the setting of the trigger II. in a bullet state. Level "Log. At the direct output of the trigger 11, arriving at the input of the request 84 of the control unit 12, causes the corresponding multiplexers of the block 15 to be locked to the sample resolution inputs. Level "Log. At the input of the request 84, the control unit 12 also causes the control inputs of the units 3 hours 14 to be set to one.

Multiplexer 9 addresses on the input connected to the inverse output of the trigger 11, a single signal switches, switching the address inputs of the block 13 and block 14 from the input address bus 19 of the device to the bus the current address of the device.

In the next, sixth cycle of the operation of the distributor 2 pulses on the leading edge of a pulse of negative polarity on the synchronous input trigger 39 is set to one state, thereby determining the beginning of the cycle of sampling the symbol code and the attribute code in the current cycle of generating a horizontal scan of the symbol.

The reading cycle of the contents of the blocks 13 or 14 of the device is similar to the write cycle.

At the command “Reading, incoming level“ Log. About the second bit of the input 21 of the device, in the cycle of forming the signals of sampling of the block 13 or 14, the seventh bit of the output 89 of the decoder 10 remains in a bullet state, and the ninth bit is set to one. Thus, the input multiplexers 51 -53, block 15 are blocked by the sampling resolution inputs.

Level "Log. 1 in the fifth bit of the output 81 of the control unit 12 performs the unlocking of the buffer register 54 of the data multiplexer 15.

The data at the input of register 54 is established through multiplexers 49 and 54, the transmission direction is determined by the state

5, the third bit of the control input of the multiplexer 15.

At the end of the cycle of sampling information from the RAM, setting the trigger 38 to a single state causes the information to be stored in the buffer register 54,

0 is at the negative edge at the recording resolution input (EW). The same signal unlocks the output buffer of the register 54 via the sample enable input (CS2) and the information read from blocks 13 or 14, set 5 inputs and outputs 22 of the device.

At the end of the reading cycle, the control device removes the command "Read and trigger 38 is reset by the signal from the first bit of output 89 of the decoder 10.

0 The buffer register 54 is locked on the sampling resolution inputs GS1 and CS2, the first of which is connected to the inverse output of the trigger 38 of the control unit 12, and the second is the inverted command Read.

5 Thus, the information reading cycle by the external control device from the screen RAM of the device ends.

Frequency divider 7, which is a counter-divider of 32, is designed to generate a frequency information

0 in order to provide a symbol flicker mode, a pseudo-symbol, a marker, etc. The flicker frequency is 1.6 Hz.

Thus, the introduction of the memory block 14, the second decoder 17, the divider 7 and the corresponding L corresponding functional links with other elements of the device allows to increase the information content of the device by allowing the formation of pseudographic characters of size

full familiarity (7X11) points of formation of a marker from one to three lines of width, as well as by providing the possibility of visual coding of information on the screen (flickering of a character or pseudo-symbol, underlining and reversing a character, getting its negative).

Claims (1)

Invention Formula A device for displaying information on a television receiver screen, comprising a first decoder, a trigger, a control unit, an address multiplexer, a first memory block, a data multiplexer, a character counter, a character generator, a television line counter, a code converter, a pulse distributor, a character string counter, a driver clock pulses, a video signal conditioner and a master oscillator, the output of which is connected to the clock inputs of the code converter and the pulse distributor, first, second, mp The third and fourth outputs of which are connected respectively to the clock inputs of the character counter, the first trigger, the clock generator and the control input of the code converter, the information of which is connected to the first output of the character generator, and the output - with the first information input of the video signal generator, whose sync input is connected to the first output, the output of which is connected to the first output, and the output of the first information generator sync pulses, the first and second address inputs of which are connected respectively with the first bit outputs of the character counter and the character counter x lines, the second output of the sync pulse generator is connected to the first information input of the address multiplexer, the third output to the input of the reset signal of the character counter, the second bit output of which is connected to the second information input of the address multiplexer, and the output of the transfer of the TV line counter input, the transfer output which is connected to the synchronous input of the counter of character rows, and the bit output is: to the first address input of the character generator, the second address input of which is connected to the first information input m-output of the data multiplexer and information input-output of the first memory block, whose address input is connected to the first output of the address multiplexer, the third information input of which is the first address input of the device, and the control input connected to the inverse trigger output, information input of which connected to the first output of the first decoder, and the direct output to the input of the request signal of the control unit and the first address input of the first decoder, the second and third address of which is are respectively an address input and a second control input device, the second output of the first decoder 0 is connected to the write and read control input of the control unit, the first output of which is connected to the reset input of the first trigger, and the second and third outputs are connected respectively to the control inputs of the first RAM block and 5 of the data multiplexer, the second information input / output of which is the information input / output of the device, the video output of which is the output of the video signal generator, characterized in that, in order to increase 0 informativeness of the device, it contains the second RAM block, the second decoder and the frequency divider, the sync input of which is connected to the transfer output of the character string counter, and the output to 5 to the first address input of the second decoder, the first output of which is connected to the address input of the character generator, and the second output - to the second information input of the video signal generator, the recording input of which is connected to the second output 0 pulse distributor, the fourth output of the sync pulse generator is connected to the reset of the counter of sign lines and the second address input of the second decoder, the third and fourth address inputs of which are connected to the second output of the character generator and the bit output of the TV lines counter, respectively, and the output of the signal generator to the first output pulse distributor, the second output of which is connected to the reset input of the control unit of the control unit, and the third, fifth and sixth outputs - from the synchronous input to the control unit group, four The fifth and fifth outputs of which are connected respectively to the control input of the second memory block and the fourth address input of the first decoder, the fifth address input of which is connected to the second output of the address multiplexer, the first output of which is ti, information input and output of which is connected to the fifth address input 0 of the second decoder and the third information input-output data multiplexer. 2 Fig.Z 5 b JIz4J M 99S9 t 6s 81 Ј-o Sh 9 gpy Z96f8fiI 2 J it 5 6 PU l K P I 3 JLLiL Zzzzza u /// bLtZL ZZZZZZZZZA / Z. s / yy / J222 V7ZZ 3 7ZZZZZZZZ2Z7Z, ЈZZZ 7ZZ7ZL 7 & 77777777 / 777U-. Sh. 77/77 // 7Л ////// Л 777777ZA / 7Z /// A : ZZZZ2 ZZZ ZZZZIZZZZL. 7/7/7/777 /, Fig.Yu 7 S one zzzzz one in km g Vyh.P5l.2 /// v // . // W /. VZ / x VHB Z, Vsh.15bl.2, 0SH.77YAL.2 Z W- Z 77 / I z. // L // A L. S /////// ZZ Out. 185ft. 2 Z22ZZZZZZZZ breath 10 Out 0. 5l eleven YZZZZZZZZZZZBbixpamdoS 3h, 5o Bbff.Q7B6 / fij9 YU WZZZY ////// MZЈZZi vn.93 ,. 9 dab 1, g & s.Sh2, r777-: 7 //// 77 7-s ROSIAOAZ . DS% of $ YEL 12    yy - - - - - - ° --Qbix. ou.Qt al it - ZZ ZZZZZZZZZZZZ. LNN OblX.Ql OL.1 & No. 8116YH. click4 J & tZZTT / T / .. : well exit.Shb