SU1583845A1 - Meter of frequency of shaft rotation - Google Patents

Abstract

The invention relates to a measuring technique and can be used in systems for stabilizing the speed of an electric drive, for example, metal-cutting machine tools, modeling stands, tape drives, etc. To improve the accuracy of measuring the shaft rotational speed, the shaft rotational frequency meter containing a rotating transformer 1, a driver 2 harmonic signals, a block of 3 formers, a generator of 4 clock pulses, a counter 5, a multiplexer 6, a register 7, a block of 3 formers consists of a phase shift comparator 8 , the generator 9 of the polling pulse, the generator 10 sync pulses, the generator 11 of the polling code and is equipped with an additional input and the first and second additional outputs, and the counter 5 is N-channel. The introduction of these blocks produces the same effect as when using multiwinding rotary transformers, however, the meter contains a conventional double-winding rotary transformer. 3 il.

Description

Fig.1

The invention relates to a measuring technique and can be used in systems for stabilizing the speed of an electric drive, for example, metal-cutting machine tools, modeling stands, tape drives, etc.

The aim of the invention is to improve the accuracy of the shaft rotation speed meter by increasing the range of measured frequencies, and increasing the speed.

Figure 1 shows the functional diagram of the shaft rotational frequency meter; Fig. 2 shows an example of execution of a block of formers for a four channel block of counters; in Fig. 3, timing diagrams explaining the operation of the shaft rotational speed meter.

The device (Fig. 1) contains a rotating transformer 1 (W), a driver of 2 harmonic signals (FGS), a block of 3 drivers (BF), a generator of 4 clock pulses (D) a block of 5 counters (CT), a multiplexer 6 (MS), a register 7 (Pr), phase-matching comparator 8 (FSK), shaper 9 write pulses (FIZ), shaper 10 sync pulses (VIF), pollator 11 of the interrogation code (FCF).

Output G4 is connected to the first input of ST5 and to the input of BT1 via FGS2, and the output of FT1 is connected to the second input of ST5 via BFZ, n outputs of CT5 are connected to the corresponding inputs of the Msb, the output of which is connected to the data input of Pr7. The FIK8 input forms the BFZ input, the FSK8 output is connected to the FSI10 input, the first output of which is connected to the BFZ output and to the FIZ input, the output of which forms the second additional BFZ output, the second FSI10 output is connected to the FC011 input, the output of which forms the first additional output BFZ ,. connected to the MCB control input, the second auxiliary output is connected to the synchronization input Pr7. An additional input BFZ formed by the second input of FSI10 is connected to the output G4.

The design of the blocks included in the BFZ (Fig. 2) depends on the selected number and channels for generating the NW code, the shaft rotation frequency. The PCF 11 is a device that implements the logical function of selecting the desired channel of code generation and can be assembled on the basis of logical elements (LE) 2AND-HE 12-14. In the general case, the FDCS includes p / 2s equipped with input phase-shifting circuits of comparators KO 15 and 16, made, for example, on the basis of an operational amplifier, FSI 10 includes itself and n synchronous triggers (T) 17-20 and n two-input logic gates ( LW) 21-24, and FIS9 is an N-input NAND gate.

FIG. 2 shows an example of the implementation of these devices for a 4-channel counter block.

The shaft speed meter operates as follows.

G4 generates a sequence of rectangular pulses C1k (Figures 1 and 3) with a frequency fg, which is fed to the first input of ST5, to the input of FGS2 and to the auxiliary input of BFZ. At the output of the FGS2, a system of sinusoidal voltages is formed to power the VT1 U (Fig 1) Uc includes two components: OS Uoc.

juos Uo "KcsinoJ0t; () luoc e iom "ks coswot,

where U is the amplitude of the sinusidal o (kc

line voltage at the output -FGS 2,

W, - frequency of power VT1, numerically equal to 2PG

silt

N,

(2)

where N is the volume of the counter, incoming

in the composition of FGS2.

At the output of the VT1, we have voltages (.Fig. 1 and 2) varying according to the law

(

1S

U1 msxc t ± rv);

1C U1M «cCOs (w, t ± pfl), (3)

where U. is the amplitude of the sinusoidal voltage at the output P is the number of pairs of poles VT1, for

simplicity P 1; in - geometric angle between

the axis of the sinus primary winding VT1 and the axis of the sinus output winding. The system of sinusoidal voltages (3) from the output of the VT1 is fed to the input of the BFZ formed by the input of the FGC8.

In the general case, for the p-channel system, FGC 8 consists of p / 2 summing two-input comparators, whose inputs are formed by two weight resistors RJ (and Rc, -, the sinus component arrives at R $, cosine - at the IC. The resistor resistances are chosen in according to expressions

R,

s in if (; os if§

(4) (5)

P

(7)

where R g- is the value of the base resistance,

  u (fi, (6)

where i is 1, 2 ... p / 2, where n is an even number of channels forming the code Hw, id is the shift angle between adjacent output signals of summing comparators, numerically equal

"," 36 °

yc

In this case, the output voltage of the comparator will be

U ;; - signfR5iU1s RcfU1c

“SignCRff-U1MaKCsin (u / dt ± 0-Kf.).

Thus, at the output of the FGC 8, n / 2 sequences of rectangular pulses are displaced relative to each other by an angle of 3lf.

As an example, consider the four-channel system. In this case, FGC 8 consists of two woofers of the HOI50 H016.

The signals from the T17-20 outputs, as shown in FIG. 2, enter FK01 1 at its DE12-14, performing the function AND-NON. At the output of the FKOI, formed by the output of the LE14 and the second input of the LE12, a polling code (vector A) is formed, consisting of two components (Figures 2 and 3 ).

but,

zs

11С

Ltc Hs xic i

(Yu) (P)

The signals from the T17-20 outputs are also fed to the inputs of the LV21-24, which are part of the FSI10. At FSI10 output, we get four sequences of clock pulses (vector L).

L,

Ji 3

.

25

thirty

20

L15 11S

L, - T

is

IS i

1C

If.

L, T

1C

 1C

(12) (13) (14) (15)

 Go

For an n-channel t system, the FSI operates in a similar manner.

From the FSI10 output, the sync pulse sequences go to the input of the vM09, formed by the inputs of the LE25, which performs the AND-NOT function. At the output of FI09, we obtain a sequence of polling pulses.

U,

c.ts

Hh

06)

At the exit of FGC 8, formed by H015, HOI6, piles U are formed,

 IS

and Ulc U 15 sigflUtS sin (oJ0t + 6) Ji

fMOKC

U

gf

signU1c «cos (oJ0t ± 6) J.

1MIX

These signals are fed to the input PSSH formed by the data inputs T17 and T18. At the output, the signal is overwritten, received by the data input, when the positive edge of the SEC (Fig. 3) arrives at the synchronization input. T19 works in a similar way. The signals T1S, T16 are generated at the outputs T17 T19 (Fig. 1-3). Similarly for T18, T20, the signals T, e, Tge are generated at their outputs (Fig. 1-3).

The vector L from the output of the BFZ formed by the first output of FSI10 (arrives at the input of the n-channel counter CT5.

Each of the n channels CT5 is a synchronous binary reversible counter 5 equipped with data inputs (input D), synchronization (input C) and recording resolution (input LCtt (j),

When a Loe input appears at the Loe input (ej of the counter of the corresponding channel of the pulse L (, L, L3 or L4 and the positive edge of the pulse of the SEC at its input C (time instant {rn. FIG. 3), the initial conditions are overwritten by the output N6 of the indicated counter. When the LI, L4, L3 or L 4 signal is removed from the input, the specified counter starts counting pulses SEC,

coming at its input C. The value of the code of the initial conditions

N.

(17)

where fr is the SEC signal frequency from G4 output

f is the frequency of the supply voltages at the input of VT1., For the time interval between two pulses at the input of Lé (the counter at its input C will receive the number N of pulses SEC

N, .fr-f-,

(18)

where f, f i f p is the frequency of the voltage U at the output of VT1. At the moment of arrival of the next positive front to the input of the counter at its output, the code N (l} 1 will take the value

fr (tfP)

AND

k /.

 N, - N,

 l + fe / f.

  f P)

U

(nineteen)

n outputs of ST5 are connected to n information inputs of the MSS, the polling code from the first additional output of the BFZ, formed by the output of FK01, comes to the control input of the MSS. The MSB performs the function of selecting one of the information channels, i.e. Depending on the value of the polling code, one of the information inputs is connected to the output of the MSS. This signal arrives at the data input of Pr7, the synchronization input of which comes from the second additional output of the BFZ formed by the FIB91 output. At the output of Pr7, the signal from the data input is overwritten at the moment t (Fig. 3) of the arrival of the positive polling pulse from the FI09 persists until the next polling pulse arrives.

t. the moment of rewriting of the code N. (j at the output of the MBU to the output of Pr7;

t write code Ne initial conditions on the output of the counter of the 1st channel ST5}

tL - the beginning of the counting of the 1st counter

channel ST5, switching the MBU, connecting the output (i + l) -ro of the channel St5 to the data input Pr7 (Fig. 3).

o

five

0

5 0 o Q

45

50

55

Claims (1)

Thus, due to the presence of n channels of forming the code K of the shaft rotation frequency, the proposed device generates the said code n times in one period of the supply bit voltages. This allows, at a fixed polling frequency, to reduce the frequency of the VT1 supply voltages and thereby increase the range of measured frequencies. Invention Formula A shaft rotation frequency controller consisting of serially connected clock pulses, a harmonic wave former, a rotating transformer, a driver unit, a counter unit and a multiplexer, the output of the clock generator also connected to the additional inputs of the driver unit and the counter unit, and the control output the driver unit is connected to the control input of the multiplexer, which is different in that, in order to increase the accuracy, a register is additionally entered into it, inline with the multiplexer, the register control input is connected to the third output of the driver unit, and the counter block is multichannel, the driver unit consists of a phase shifter, a clock generator, a polling code generator, a write pulse generator, and the phase shifter input forms the input block of the formers, the output of the phase-shifting comparator is connected to the input of the clock generator, the first output of which is connected to the output of the The second output of the sync pulse generator is connected to the input of the polling code generator, the output of which forms the control output of the imaging block connected to the control input of the multiplexer, the second input of the sync pulse generator forms an additional input block shapers and connected to the output of the clock generator. )