SU1575310A1 - Controllable counting device - Google Patents

Abstract

The invention relates to automation, pulse and computer technology and can be used in information input devices. The purpose of the invention is to enhance the functionality by allowing the code to be reduced by any given number. The device contains adders 1 and 2 modulo 2, decoders 3 and 4, blocks 5-7 of memory, subtraction element 8, elements AND 9 and 16, blocks of elements AND 10 and 11, element OR 12, elements NOT 13 and 14, an encoder 15 and an OR-NOT element 17. The device provides operation in addition and subtraction modes with subtraction of a given number from a previously accumulated code. 3 il.

Description

The invention relates to automation, pulse and computer technology and can be used in devices for servicing applications in the order they are received, in devices for inputting information from various discrete sensors to a processing device, or to a control machine.

The aim of the invention is to expand the functionality of the device by providing the ability to reduce the code by any given number.

Figure 1 shows the structural diagram of the proposed device; figure 2 is a functional diagram of the device for η = 3 (η is the maximum number of pulses to be counted) and K = 2 (n £ 2 ^k ); in FIG. 3 is a table explaining the operation of the device.

In Fig. G and 2 are indicated: 1 and 2 adders; 3 and 4 - binary decoders; 5-7 - memory blocks, 8 - subtraction element; 9 - the first element And; 10 and 11 - blocks of elements And; 12 element OR; 13 and 14 - elements NOT ', 15 - binary encoder; 16 - the second element And; 17 - element OR-NOT.

In adder 1 modulo two per. the first K-1 inputs of the first group of summing inputs are connected to the housing (0), and the last K-th input is connected to the first input of the device, the inputs of the second group of summing inputs are connected to the corresponding outputs of the binary encoder 15, the inputs of which are connected to. the first group of inputs, devices. The outputs of adder 1 are connected to the corresponding inputs of the first group of summing inputs of adder 2 · modulo two, the inputs of the second group of summing inputs of which are connected to the corresponding outputs of block 11 of elements I. The outputs of adder 2 modulo two are connected to the corresponding inputs of binary decoder 3, the outputs of which are connected to the corresponding inputs of the first group of inputs of block 5 of the memory. The outputs of the memory unit 5 are connected to the corresponding inputs of the reduced number of the subtraction element 8 modulo two, the first K-1 of the inputs of the subtracted number of which are connected to the housing (O ”), and the K-th input - with the second input of the device, the input of the element is NOT 13 and the first and second inputs of the element OR 12.

' four

The first input of the OR element 12 is connected to the first input of the device, and the output is from the (K + 1) -th input of the block of 10 AND elements, the first K inputs of which are connected to the corresponding outputs of the subtraction element 8 modulo two and the corresponding inputs of the OR-NOT 17 element, and the outputs - with the corresponding inputs of the binary decoder 4. The outputs of the decoder 4 are connected to the inputs of the memory unit 6 as follows: the first output of unit 4 with the second input of the memory unit 6, ..., (p-1) -th output - with η-th input, and the first input of the memory unit 6 is connected to the output of the element And 9, the second input is a cat It is connected to the output of the element OR NOT 17. The outputs of the memory unit 6 form the first group of device outputs and are connected to the corresponding inputs of the second group of inputs of the memory unit 5 and the corresponding inputs of the memory unit 7, the outputs of which are connected to the corresponding inputs of the unit. 11 elements I. The first input of the device is connected to the (K + 1) th input of the block of 11 AND elements, and the input of the HE 14 element, the output of which is connected to the second input of the AND 16 element, the first input of which is connected to the output of the HE 13 element and input C block 5 of the memory, and the output with the input From block 7 of the memory.

Blocks 10 and 11 of the elements AND are identical. Block 10 of the elements And (figure 1 and 2) contains K elements And 10-1, ..., 10-K. The first inputs of all AND elements are connected to the K · ’· 1st block input, the second inputs are with the corresponding block inputs, and the outputs are with the corresponding block outputs. The memory block 6 (figure 2) contains K D-triggers 6-1 and 6-2 and 2K elements OR 6-3, 6-4, 6-5 and 6-6, the inputs of which are connected to the inputs of the first group of inputs of the block as follows way: the first input of the block with the first inputs of the OR elements 6-4 and 6-6, the second input of the block with the second input of the OR 6-4 elements and the first input of the OR 6-5 element, the third input of the block with the first input of the OR element 6- 3 and the second input of the OR element 6-6, the fourth input of the block with the second inputs of the elements OR 6-3 and 6-5. The outputs of the elements OR 6-3 and 6-4 are connected respectively to the S and R inputs D of the trigger 6-1, and the outputs of the elements OR 6-5 and 6-6 are respectively connected to S and

R inputs of the D-trigger 6-2. Q-outputs of D-flip-flops 6-1 and 6-2 are connected respectively to the first and second outputs of the block.

The memory unit 7 (figure 2) contains K D-flip-flops 7-1 and 7-2, and the C-inputs of all the triggers are connected to the C-input of the block. D-input of the trigger 7-1 is connected to the first input of the block, and the Q-output to the first output of the block. D-input of trigger 7-2 is connected to the second input of the block, and Q-output is connected to the second output of the block.

The memory unit 5 (FIG. 2) contains K D-flip-flops 5-1 and 5-2 and OR elements 5-3 and 5-4, and the C-inputs of the triggers are connected to the C-input of the block. The first input of the first group of inputs of the block is connected to the R-input of the trigger 5-1 and the first input of the OR element 5-4, the output of which is connected to the S-input of the trigger 5-2. The second input of the first group of inputs of the block is connected to the R input of the trigger 5-2 and the second input of the OR element 5-3, the output of which is connected to the S-input of the trigger 5-1. The third input of the first group of inputs of the block is connected to the second inputs of the elements OR 5-3 and 5-4. The first input of the second group of inputs of the block is connected to the D-input of trigger 5-1, and the second input of the second group of inputs is connected to the D-input of trigger 5-2. Q-outputs of triggers 5-1 and 5-2 are connected respectively to the first and second outputs of the block.

Consider the operation of the device for the case η = 3 and K = 2 (n- <2). In this case, there is no need for a binary encoder 15 (Fig. 1), since K = η = 1. In the initial state, the triggers of all memory blocks are in the state 0. In the event that the first information pulse and the pulse at the fourth input of the device appear on the first input 18 of the device, which corresponds to the Add two to the recorded unit command, number two (Fig. C) ^ on the first group the summing inputs of adder 1 modulo two appears combination (01), and on the second group of summing inputs - combination (10), the summing result combination (11) = 3-- goes to the first group of summing inputs of adder 2 modulo two, and since trigger If the memory block 7 is in state 0, then the second group of summing inputs has a combination (00). The summation result - combination (11) - from the output of the block goes to the outputs of binary 5 of the decoder 3, the signal from the output of which through the element OR 5-3 goes to the S-input of the D-trigger 5-1 and sets it to state. 'H, the same signal through the OR element 5-4 goes to the S-input of D-flip-flop 5-2 and sets it to state 1. Thus, in block 5 of the memory, combination (11) is written and from the outputs its potentials are fed to the inputs of the reduced number of the subtraction element 8 modulo two, at the inputs of the subtracted number of which there is a combination of (00). From the outputs of element 8, the result of the subtraction, combination 20 (11), is bitwise fed to the second inputs of the corresponding elements AND of the block 10 of the AND elements, the first inputs of which from the first input of the device through the element OR 12 25 receive the same information pulse. From the output of the block of 10 elements AND the result of the subtraction - combination (11) - is supplied in pulse form to the inputs of the binary decoder 4, 30 pulse from the output of which is received. to the input of the memory unit 6 and through the OR element 6-3 to the S-input of the trigger 6-1 and sets it to state 1, and through the OR element 6-5 to the S-input 35 of the trigger 6-2 and sets it to 1 ” . · The recorded combination (11) from the outputs of memory block 6 goes to the first group of device outputs, 1 from the first output 40 of memory block 6 to the D-inputs of triggers

7-1 and 5-1, and 1 from the second output of the memory unit 6 to the D-inputs of triggers 7-2 and 5-2. An inverted information pulse arrives at the 0 input of the memory unit 7. The trailing edge of the information pulse triggers 7-1 and 7-2 of the memory unit 7 are set to state 1 and potentials 1 appear on the first and second inputs of the block of elements And 50.

In the case of the appearance of the first subtraction pulse at the second input of the device, it enters the input 19 of the inputs of the subtracted number of the subtraction element 8 modulo two and, since the first input is constantly present, 0 is present, a combination of (01) = 1 is organized at these inputs. At the inputs of a reduced number of potentials from the outputs of the memory unit 5 there is a combination (11). The result of the subtraction, combination (10), is fed to the inputs of the block of 10 AND elements, the input of which through the OR element 12 receives a decisive pulse from the second input of the device. The combination (10) in pulse form is supplied to the inputs of the binary decoder 4, from the second output of which through the OR element 6-3 it is supplied to the S-input of the trigger 6-1, which remains in the 1 * 'state, and through the OR element 6-6 - to the trigger R input

6-2 and the leading edge of the subtraction pulse sets it to state 0. Thus, the combination (10) is present at the outputs of the memory unit 6 and the outputs of the device with potentials. 1 from the output of block 5 of the memory goes to the D-inputs of triggers

7-1 and 5-1, and 0 from the output of memory unit 5 to the D-inputs of triggers 7-2 and 5-2. The inverted subtraction pulse arrives at the C-inputs of all the triggers. The trailing edges of the subtraction pulse trigger 7-2 and 5-2 are set to state 0, the triggers 7-1 and 5-1 remain in state 1. At the inputs of the block. 11 elements And receives potentials combination (10).

If a second information pulse appears at the first input of the device and there are no pulses at the device inputs 20 and 21, the adder 1 modulo two sums the combination (01) from the first group of summing inputs with the combination (00) from the second group of summing inputs. The summation result, combination (01) from the block outputs goes to the first group of summing inputs of adder 2 modulo two, to the second group of summing inputs through elements And 11-1 and 11-2, according to the enable signal, the combination (10) comes from the first input of the device. The summation result - a combination of (11) - arrives at the inputs of the binary decoder 3, the output of which through the elements OR 5-3 and 5-4, the signal goes to the S-inputs of triggers 5-1 and 5-2. The trigger 5-1 remains in state 1, and the trigger 5-2 by the leading edge of the information pulse goes into state 1. From the output of the memory unit 5, the combination (11) is supplied to the inputs of the reduced number of the subtraction element 8 modulo two, at the inputs of the subtracted number of which there is combination (00). The result of the subtraction, combination (11) is supplied to the inputs of the block of 10 AND elements and, with an enable pulse from the OR element 12, is passed to the inputs of the binary decoder 4, from the output of which, through the OR elements 6-3 and 6-5, the signal goes to the S-inputs of triggers 6-1 and 6-2 and the leading edge of the information pulse, trigger 6-2 is set to state 1. At the outputs of the memory unit 6 and the device, a combination (11) appears. This combination is fed to the D-inputs of the corresponding triggers of the memory unit 7, to the Inlet of which an inverted information signal is supplied. The back of the information pulse trigger 7-2 is transferred to state 1. The combination (11) from the outputs of block 7 of the memory is fed to the inputs of block 1 G elements I.

δ in the case of the appearance of a second subtraction pulse, the combination (11) is present at the inputs of the reduced number of the element 8 of the subtraction modulo two., the result of the subtraction is the combination (10) through the block of 10 elements AND arrives at the inputs of the binary decoder 4, the output of which is through the element OR 6 -3 the signal is fed to the S-input of the trigger 6-1, and through the element OR 6-6 - to the R-input of the trigger

6-2, which is set to the position 0 by the leading edge of the subtraction pulse. At the device outputs, a combination (10) appears, which is bitwise fed to the D inputs of the corresponding triggers of memory blocks 5. And 7. Triggers 5-1 and 7-1 remain in state 1, and triggers 5-2 and

7- 2 trailing edge of the subtraction pulse are set to state 0

When the third impulse of subtraction arrives from the number (10) recorded in the memory unit 5, the number (01) is subtracted. The result of the subtraction - combination (01) - the leading edge of the subtraction pulse is recorded in the triggers of block 6 and the trailing edge of the subtraction pulse is overwritten in the memory blocks 5 and 7.

When the fourth subtraction pulse arrives from the combination (01) recorded in the memory unit 5 in the subtraction element 8 modulo two, the addition and subtraction of the invention are subtracted by the counting device, combination (01). The result of the subtraction - the combination (00) - is fed to the inputs of the OR-NOT 17 element, ”1 from the output of which is fed to the second input of the AND 9 element, the first input of which is supplied from the second input of the device by the subtraction pulse. From the output of the And 9 element, the pulse goes to the first input of the memory unit 6 and through the OR 6-4 and 6-6 elements to the S-inputs of the triggers 6-1 and 6-2 and sets them to the zero state by the rising edge. At the outputs of the device, there is a combination of 00 and at the · D-inputs of all the triggers of memory blocks 5 and 7 there is 0. The trailing edges of the memory blocks 5 and 7 are set to the zero position on the trailing edge of the subtraction pulse.

Thus, an account is provided in the NII modes.

Claims (1)

Formula A controlled device containing a <backup and second adders, a decoder, a memory block, while the last input of the first group of summing inputs of the first adder is connected to the first input of the device, all other inputs of this group are grounded, the outputs of the first adder are connected to the inputs of the first group of summing inputs of the second adder, outputs which is connected to the inputs of the decoder, the outputs of which are connected to the inputs of the memory unit, characterized in that, in order to expand the functionality by providing the possibility of reducing to An ode to any given number, a second decoder, a second and third memory blocks, a subtraction element, a first and second AND element, a first and second block of an AND element, an element are additionally introduced into it. OR, the first and second elements are NOT, the encoder, the element is NOT, while 1575310 10 outputs of the first memory block. Connected to the inputs of the reduced number of the subtraction element, the last input of the group of inputs of the subtracted number of which is connected to the second input of the device, and the other inputs of this group of inputs are grounded, the outputs of the subtraction element are connected to the corresponding inputs of the first block of elements And and the inputs of the element OR NOT, the output of which is connected to the second input of the first AND element, whose first input is connected to the second input of the device, and the output - to the first input of the second memory block, the other inputs of which are connected s with the corresponding outputs of the second decoder, the inputs of which are connected to the outputs of the first block of AND elements, (K + 1) -th input of which is connected to the output of the element is connected to the first input of the device, and the second input of the device and the input of the first element are NOT, the output of which is connected to clock input by the first memory block and the first input of the second AND element, the second input of which through the second element is NOT connected to the first input of the device, and the output to the clock input of the third memory block, the inputs of which are connected to the corresponding outputs of the second of the memory block by the group moves, the yen outputs from the second block of elements And, the (K + 1) -th input of which is connected to the first input of the device, and the outputs are connected to the inputs of the second group of summing inputs of the second adder, the inputs of the first group of device inputs are connected to the encoder inputs, the outputs of which are connected to the second group of summing inputs of the first adder. OR, whose first input is with a second input, devices and inputs of the second inputs of the first memory block, of the third memory block with associated inputs