SU1575125A1 - Apparatus for measuring the ration of two voltages - Google Patents

Abstract

This invention relates to electrical measuring technology. The purpose of the invention is to improve the measurement accuracy. The device contains the sources 26 and 27 of the linearly varying signal, the source 3 of the reference voltage, the comparator 6, the key 7. The execution of the source 26 on the analog-to-digital converter (ADC) 21, the register 18, the counter 4 pulses and controlled frequency divider 9, execution source 27 on the ADC 22, register 19, the pulse counter 5, controlled frequency divider 10, digital-to-analog converter 11, digital comparator 6, as well as introduction to the ADC device 23, register 20, pulse generator 13, key 8, trigger 12 and elements 14-17 delay provided the achievement of the goal as a result of the implementation of the device on the digital element base. 1 il.

Description

This invention relates to electrical measuring technology.

The purpose of the invention is to improve the measurement accuracy.

The drawing shows a functional diagram of the device.

The device contains the first 1 and second 2 inputs, the source 3 of the reference voltage, the first 4 and second 5 pulse counters, digital comparator 6, the first 7 and second 8 keys, the first 9 and second 10 controlled pulse frequency dividers, a digital-analog converter (DAC) 11, trigger 12, the generator 13 pulses, the first - the fourth delay elements 14-17, the first - the third registers 18-20, the first - the third analog-to-digital converters A / D converters 21-23, input 24 Start and output 25 devices. The blocks 4,9,18 and 21 form the first source 26 of the linearly varying signal, and the blocks 5,10,11, 19 and 22 form the second source 27 of the linearly varying signal. The input 1 of the larger measured voltage U6) f is connected to the input of the A / D converter 21, the output of which through the register 18 is connected to the preset input of the counter 4, the output of which is connected to the first input of the comparator 6, the second input of which is connected to the output of the register 20. The input of the register 20 connected to the outputs of the ADC 23, the input of which is connected to the input 2 of the lower measured voltage UBx (U cx b in). Output

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source 3 is connected to the input of the ADC 22 | whose output through the register 19 is connected to the preset input of the counter 5, the output of which is connected through the serially connected CLP 11 and the key 7 is connected to the output 25 of the device. The output of the generator 13 through the key 8 is connected to the inputs of dividers 9 and 10 of the frequency, the output of the first of which is connected to the counting input of the meter 4 directly and to the building input of the comparator 6 via element 14, and the output of the second to the counting input of the counter 5 .

The control input of the divider 9 is connected to the output of register 18, and the control inputs of the divider 10 to the output of register 19. Input 24 Start is connected to the reset inputs of counters 4 and 5 directly, to the control inputs through element 15 and to the start input of the generator 13 through element 17. The output of element 15 is connected to the reset input of trigger 12 via element 16, the installation input of trigger 12 is connected to the output of comparator 6. The inverse output of trigger 12 is connected to the control input of key 8, and its direct output is connected to the control at the key input 7. The input of the first source is 26 linear from the changing signal forms the ADC 21 input, the clock input of the divider 9 input, the control input — the control input of counter 4, the reset input — the reset input of counter 4, the output — output of counter 4, strobe output — the output of divider 9. The second source input 27 linearly varying signal forms the input of the ADC 22, the clock input - the input of the divider 10 control input - the control input of the counter 5, the reset input - the reset input of the counter 5, the output - the output of the DAC 11. The device works as follows.

In the initial state, counters 4 and 5 are set to zero, keys 7 and 8 are open. In register 18, after converting the voltage A / D converter 21 from input 1, the value Ujx is entered into register 20 after converting voltage A / D converter 23 from input 2, the value Uex is entered in register 19 after conversion of the voltage converter 3 A / D converter 22 to U0l. At the output 25 of the device, the signal is zero.

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Upon arrival at input 24 of the device start pulse, the zero status of the counters 4 and 5 pulses is confirmed, and the time interval defined by delay element 15, the register 18 is entered into the counter 4, and the register 19 enters the counter 5, after the time interval C .., determined by the delay element 17, the pulse generator 13 begins to generate a sequence of clock pulses at the output, the trigger 12 is set to zero after a time interval C defined by the delay element 16 (Cj). When the trigger 12 is set, the key 8 closes and a pulse is received at the inputs of dividers 9 and 10. from the generator output 13 pulses. The counting inputs of counters 4 and 5 receive pulses, the frequency of which is proportional to the values of UВх and Ъ, respectively. When each successive pulse arrives at the input of the counter 4, the same pulse delayed by the delay element 14 is fed to the input of the comparator 6. When the pulses arrive at the counting input (subtracting input) of the counter 4, the contents of the counter decrease. When the contents of counter 4 and register 19 are equal, a pulse appears at the output of comparator 6, which arrives at the input of trigger setup 12. In this case, a single potential is fed to the input of key 7, key 7 closes, and key 8 opens. Pulses from the generator output 13 pulses when the key 8 is closed through the pulse frequency divider 10 also arrive at the counting input of the counter 5, reducing its content. When the switch 7 is closed, the contents of the counter B, after being converted to analog form by means of a DAC 11, arrive at output 25, where a voltage is fixed proportional to the ratio of the smaller measured voltage -1 to the larger. Since simultaneously with the closure of the key 7, the key 8 is opened, the pulses from the output of the generator 13 do not arrive at the inputs of dividers 9 and 10, which means that the contents of the counters 4 and 5 do not change. When a pulse arrives at input 24 Start, the counters are reset to zero and set through 1 the contents of counters 4 and 5 equal to U HF and U01, respectively, after

232, the trigger 12 is set to zero, and at the output of the generator 13, after a time of E7 1, a sequence of clock pulses begins to form.

Claims (1)

Invention Formula A device for measuring the ratio of two voltages, containing the first source of a linearly varying signal, whose input is connected to the first input of the device, and the output to the first input of a comparator, the second source of a linearly varying signal, whose input is connected to the reference voltage source, and output to the output of the device through the first key, the second input of the device is connected to the second input of the comparator, and the input of the start of the device is characterized in that, in order to improve the accuracy, the first source of the linearly varying signal is The first analog-to-digital converter (ADC), the first register, the first pulse counter and the first-controlled frequency divider, the second source of the linearly varying signal is made on the second ADC, the second register the second pulse counter, the second controlled by the frequency divider and digital A analog converter (D / A converter), and the comparator is digital, with the third ADC, third register, second key generator, trigger, and four delay elements, the first ADC input connected to the first source input l variable output signal and the output to the preset input of the first pulse counter and the control input of the first controllable frequency divider, the output of which is connected to the counting input of the first pulse counter and the gate output of the first source of the linearly varying signal, and the input to the clock 0 five 0 five 0 five 0 five 0 " the input of the first source of linearly varying signal, the output, control-1 input and the reset input of the first pulse counter are connected respectively to the output, control input and the reset input of the first source of linearly varying voltage, the input of the second ADC is connected to the input the second source of the linearly varying signal, and the output with the preset input of the second pulse counter and the control input of the second controlled frequency divider, the output of which is connected to the counting input of the second pulse counter, input - to the clock input of the second source of the linearly varying signal, the output of the pulse counter is connected to the input of the DAC, the output of the DAC, the control input and the reset input of the second pulse counter are connected respectively to the output, the control input and the reset input of the second source of the linearly varying signal, the third ADC and the third register connected in series are connected to the disconnection of the second input of the device and the second input of the comparator, the gate input of which is connected to the gate of the first source linearly varying state signal through the first delay element, and the output to the trigger setup input. The device start-up is connected to the reset inputs of the first and second mentioned sources directly to the control inputs of these sources through the second delay element, and to the trigger input of the pulse generator through the fourth delay element, the output of the pulse generator is connected to the clock inputs of these sources through a second key, the control input of which is connected to the inverse output of the trigger, the direct output of the trigger is connected to the control the primary input of the first key, and the reset input with the output of the second delay element through the third delay element. 7 25