SU1571784A1 - Generator of three-level digital signal - Google Patents

Abstract

The invention relates to digital signal regenerators for information transmission systems. The goal is to improve the accuracy of the registration of pulses by level. The input signal, after being amplified by amplifier 1 with an automatic adjustment unit 2 in the feedback circuit, is rectified in rectifier 3 and filtered in a constant-phase discharger 4. To separate the pulses of positive and negative polarity to the inputs of the first and second coincidence units 7 and 8, the signal is applied through the first and second comparators 5 and 6. Information symbols are registered in the first and second decision blocks 9 and 10 under the action of pulses from the output of the synchronization unit. 2 Il.

Description

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The invention relates to radio engineering and communications and can be used in digital information transmission systems.

The purpose of the invention is to improve the accuracy of pulse level detection.

FIG. Figure 1 shows the structural electrical circuit of the three-level digital signal regenerator; in fig. 2 - voltage plots showing the operation of the regenerator.

The regenerator contains a correction amplifier 1, an automatic gain control unit 2, a rectifier 3, a constant component removal unit 4, the first 5 and second 6 comparators, the first 7 and second 8 matching blocks, the first 9 and second 10 decision blocks, the first 11 and the second 12 pulse shapers, the adder 13 and the block 14 synchronization.

Regenerator three-level digital signal works as follows.

The input of the regenerator comes - a three-level digital signal. FIG. 2 b shows one of the possible (the NDS digital signal implementations on

the output of the corrective amplifier 1 with the block 2 in the feedback circuit corresponding to the original signal shown in FIG. 2a The probability of occurrence of information units in a digital signal (positive and negative) is equal to half, and the pulses occupy the entire clock interval. Under these conditions, the digital signal at the output of the rectifier 3 contains a constant component equal to half the height of the undistorted pulse. Thus, the level of the constant component is equal to the level of the optimal threshold of the comparators in absolute value (see Fig. 2c and 26). Such a signal-after passing through block 4 has the form shown in FIG. 2g. The second input of the first comparator 5 is grounded, it compresses the signal at the zero level and as a result rectangular impulses of average width equal to the duration of the clock interval appear in its output (see Fig. 2d). At the same time, the signal from the output of the correction amplifier 1 is fed to the first the input of the second comparator 6, the second input of which is grounded. The second comparator 6 compares

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a positive half-wave of a digital signal, as a result, positive pulses appear at its output with an average duration equal to approximately the duration of two clock intervals (see Fig. 2e). To separate the positive and negative half-wave pulses into the two inputs of the first block 7, pulses are sent from the direct outputs of the first 5 and second 6 comparators, and the two inputs of the second block 8 are pulsed from the direct output of the first comparator 5 (see Fig. 2e) and the inverse output of the second comparator 6 (see Fig. 2i), as a result, pulses appear at the outputs of the first 7 and second 8 blocks (see Fig. 2k and 2l), which are then fed to the information inputs of the corresponding first 9 and second 10 decision blocks, where is the registration of these imps Ls, at clock points of time, set by clock pulses from the output of block 14 (Fig. 2m). From the outputs of the first 9 and second 10 decision blocks, the pulses are fed to the corresponding first 11 and second 12 drivers, from whose outputs the normalized information pulses are normalized in height and in duration through the adder 13 to the line (Fig. 2n).

Claims (1)

Invention Formula A three-level digital signal regenerator containing a correction amplifier with an automatic gain control unit in the feedback circuit, the first and second comparators, the second of which is connected to the output of the correction signal The first and second decision blocks, whose outputs through the corresponding first and second pulse formers are connected to the inputs of the adder, as well as the synchronization block, the input of which is connected to the output of the first comparator, characterized in that , the first and second blocks of coincidence are inserted and connected between the output of the correction amplifier and the input of the second comparator are a series-connected rectifier and a constant-phase stripper, with the output of a comparator connected to the combined first inputs of the first and second coincidence blocks whose outputs are connected to inputs of the respective first and second decision block, control inputs which are combined and connected to the output of the synchronization unit, and the direct and inverse outputs of the second comparator are connected to the second inputs of the first and second matching blocks, respectively. S  LlJJLLLLJa LLi n Figg