SU1566475A1 - Comparator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices comparing the electrical parameters of signals. The aim of the invention is to improve the accuracy. For this, the comparator contains a subtraction unit 1, the first and second inputs of which are device inputs, trigger regenerator 2, input stage 3, first and second drivers 4 and 5 supply current pulses, delay elements 6 and 7, one-shot 8 and D-flip-flop 9 2 zp f-ly. 6 Il.

Description

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figure 1

The invention relates to a pulse technique.

The aim of the invention is to improve the accuracy.

FIG. 1 shows a functional diagram of the device; Figures 2 and 3 are respectively schematic diagrams of a trigger regenerator and a power supply current driver; in fig. 4 - plot at the entrance UtTp and blocks 4, 5, 8; in fig. 5 and 6 are schematic diagrams of the subtraction unit and the output stage, respectively.

The comparator (Fig. 1) contains a subtraction unit 1, the first Uem and the second and VC2 inputs of which are the first and second inputs of the device, and the outputs are connected to the inputs of the trigger regenerator 2, the output stage 3, the two driver 4 and 5 supply current pulses, the input of the first of which is the third input of the Ucrp device, two delay elements 6 and 7, a single-oscillator 8 and a D-flip-flop 9. The first output of the trigger regenerator 2 is connected to the first input of the output stage 3. The first output of the first Shaper 4 power supply pulses is connected to the third input block 1 is subtracted, and the second is through the first element

6-delays with the input of the second driver 6 of the supply current pulse, the first output of which is connected to the third input of the trigger regenerator 2, the second output through the second element

7 delays to the input of the one-shot 8, the output of which is connected to the synchronization input of the D-flip-flop 9. The second output of the trigger regenerator 2 is connected to the second input of the output stage 3, the output of which is connected to the information input 1 -trig: hera 9. Output

D flip-flop 9 is the output bus of the device. The trigger regenerator 2 is made of transistors 10-J3, resistors J4-20 and a capacitor 21, the base of the first transistor 10 being connected to the base of the second transistor J1 by the first terminals of the capacitor 21 and the first 14 and second 15 resistors, the emitter of the first transistor 10 is first the input of the trigger regenerator 2 and connected to the first output of the third resistor 16 and the collector of the third transistor 12, the collector of the first transistor 10 is the first output of the trigger regenerator 2 and is connected to the first output

5 0 5 0

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five

the fourth resistor 17 and the base of the fourth transistor 13, the collector of which is the second output of the trigger regenerator 2 and connected to the first output of the fifth resistor 18 and the emitter of the second transistor 11, the collector of which is the second output of the trigger regenerator 2 and connected to the first output of the sixth resistor 19 and the base of the third transistor 12, the emitter of which is combined with the emitter of the fourth transistor 13 and is the third input of the trigger regenerator 2, the second output of the third resistor 16 is connected to the first output variable resistor 20, the second output of which is connected to the second output of the fifth resistor 18, the middle output (slider) is combined with the second output of the capacitor 21 and the second output of the first resistor 14 and is connected to the power supply line of positive polarity + ipit. 15, fourth 17 and sixth 19 resistors are connected to the common bus.

The first 4 and second 5 supply current pulse drivers are made on transistors 22-24, capacitors 25 and 26 and resistors 27-33, the first terminal of the first resistor 27 being the input of the driver 4 (5) of the supply current pulse and connected to the first output of the capacitor 25 The second terminal of which is connected to the first terminals of the second 28 and third 29 resistors and the base of the first transistor 22, the emitter of which is connected to the emitters of the second 23 and third 24 transistors and the first terminals of the fourth resistor 30, the collector to the first terminal of the fifth resistor 21 and the first output of the second capacitor 26. The second output of the capacitor 26 is connected to the bases of the second 23 and third 24 transistors and the first output of the sixth 32 and seventh 33 resistors. The collectors of the second 23 and third 24 transistors are respectively the first and second outputs of the driver 4 (5) of the supply current pulse, the second terminals of the second 28, fifth 31 and seventh 33 resistors are connected to the common bus, the second terminal of the first resistor 27 is connected to the source bus positive polarity + ipit voltage, and the second outputs of the third 29, fourth 30 and sixth

51566475

32 resistors - to the power supply voltage of the negative polarity -type.

The comparator works as follows.

In the initial state at the input U, the driver 4 is maintained

logical signal O, at which the output currents of the drivers 4 and 5 are equal to zero. Here, the subtraction unit 1 and the trigger regenerator 2 are in the off state. Thus, the current in all the circuits of blocks 1 and 2 responsible for the accuracy of the operation of the device is equal to O A and only in them is not allocated.

After the logical signal appears at the input of the imaging device 4, current pulses 14 and 14 of a certain duration are formed at its outputs (Fig. 4). The current pulses from the first output of shaper 4 are fed to the third input of block 1 subtraction, it

ten

15

20

two times, namely, the time of setting the output signal in the block and the time required for reliable triggering of the trigger regenerator 2 (in the layout, the total time is only 100 not). The pulse duration on the first output of the imaging unit 5 is selected similarly with respect to blocks 2, 3, and 8 (in the layout, a delay of 40 n is not a duration of 150). The choice of single-pulse pulse parameters depends on the type of chip used as D-flip-flop 9 (in layout 200 With a duty cycle (ratio of

repetition signal at the input UЈ

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strobe pulse duration) not less than ten elements, on which drift depends (transistors in blocks 1 and 2), do not have time to warm up with current and, therefore, do not have different heating, therefore there is no heat loop. The accuracy of the proposed comparator is improved compared to

turns on and forms at outputs sig-25 with known, and power consumption

) decreases.

cash proportional to the difference in input voltages. With the passage of a current pulse from the second output of the imaging unit 4 through the delay element 6, the pulse is delayed by the time the signal is set at the output of the subtraction unit 1. At the outputs of the imaging unit 5, two current pulses 15 and I j are produced. longer duration. The current pulse arriving from the first output of the shaper 5 to the third input of the trigger regenerator 2 switches on the last and its outputs set logical signals corresponding to the difference of signals at the inputs of the trigger regenerator 2. The output stage 3 converts the output levels of the trigger generator to standard ( for example, TTL) levels. The output signal of the cascade 3 is fed to the information input of the D-flip-flop 9. The current pulse from the second output of the driver 5 passes through the second element 7 of the delay

 where it is delayed by the time the signal is established (Fig. 4) at the information input of the D-flip-flop 9. Then the pulse arrives at the input of a single-vibrator 8, which forms a strobe-pulse, on the leading front of which information about the sign of voltage difference at the inputs U in (and the UBXc device is entered in the D-flip-flop 9. The pulse duration at the first output of the shaper 4 is determined by the sum of

0

five

two times, namely, the time of setting the output signal in block 1 and the time required for reliable triggering of the trigger regenerator 2 (in the layout, the total time is 100 not). The pulse duration at the first output of the imaging unit 5 is selected similarly with respect to blocks 2, 3 and 8 (in the layout, the delay is 40 n, the duration is 150 n). The choice of the parameters of a one-shot pulse depends on the type of chip used as D-flip-flop 9 (not 200 in the layout). When the duty cycle (the ratio of the period

repetition signal at the input UЈ

GR

the duration of the strobe pulse is not less than ten elements on which the drift depends (transistors in blocks 1 and 2) do not have time to warm up with current and, therefore, do not have different heating, therefore there is no heat loop. The accuracy of the proposed comparator is improved compared to

with known, and the power consumption

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) decreases.

The trigger regenerator works as follows.

In the initial state, the same currents flow through transistors 10 and 11 (Fig. 2), which, flowing through resistors 17 and 19, create the same voltage on the bases of transistors 12 and 13. When the input signal arrives from block 1, the symmetries of transistors 10 and 11 is violated, because in one of the emitter circuits of these transistors (for example, transistor 11) the current increases due to the input current of unit 1. Transistor 11 is locked (the degree of locking depends on the input current) and the voltage at the base of transistor 12 is lower than the e.

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When a current pulse 1 appears from the first output (FIG. 2) of the Former 5, the current flows through the transistor 13, since its base is under

higher potential. The voltage drop across the resistor 18 increases, the transistor 11 is completely locked, and the voltage at the base of the transistor 1 2 and the second output is the rigger

the register drops to ON, and at the first output and base of the transistor 13, the potential is still positive. The signals at the outputs of the trigger regenerator 2 are stored to

the current pulse terminations from Shaper 5. Resistors 14 and 15 are used to set the required potential at the bases of transistors JO and J1, and the capacitor 2J to reduce voltage fluctuations at the bases of said transistors when changing their base currents.

Shaper 4 (5) current pulse

(Fig. 3) works as follows. The input signal forms a voltage pulse at the junction of resistor 27 and capacitor 25. The latter is differentiated and fed to the base of transistor 22, the potential of which is set by a divider from resistors 28 and 29. On the collector of transistor 22 a triangular pulse is formed, which differentiates again on capacitor 26, increases the potential of the bases of transistors 23 and 24 for a certain time , and current pulses are generated on the collectors of transistors 23 and 24. FIG. Figures 5 and 6 show the possible implementations of block 1 of the subtraction and the output cascade 3. Element 6 (7) of the delay can be a capacitor.

Claims (3)

1. A comparator containing a subtraction unit, the first and second inputs of which are the first and second sockets of the comparator, and the outputs are connected to the inputs of the trigger regenerator, the first and second outputs of which are connected respectively to the first and second inputs of the output stage, of which By the fact that, in order to increase the accuracy, two pulse current supply drivers were introduced into it, the input of the first of which is the third input of the Comparator, two delay elements, a one-shot and a D-flip-flop, and the first output of the first driver the supply current pulses are connected to the third input of the subtractor, and the second through the first delay element to the input of the second driver of the current supply pulses, the first output of which is connected to the third input of the trigger regenerator, the second output through the second delay element, the output of which is connected to the synchronization input of the D-flip-flop, the output of the output stage is connected to the information input of the D-flip-flop, the output of which is the output bus of the comparator. 2. The comparator according to claim 2, wherein the trigger regenerator is made of four transistors, seven resistors and one capacitor, the base of the first transistor connected to the base of the second transistor, with the first terminals of the capacitor and the first and second resistors, the emitter of the first transistor is first the trigger input of the regenerator and connected to the first output of the third resistor and the collector of the third transistor, the collector of the first transistor is the first output of the trigger regenerator and is connected to the first output One fourth resistor and a fourth transistor base, the collector of which is the second input of the trigger regenerator and connected to the first view of the fifth resistor and the second Granzistor's emitter, whose collector is the second output of the trigger regenerator and connected to the first output of the sixth resistor and the base of the third transistor, the emitter of which is combined with the emitter of the fourth transistor and is the third input of the trigger regenerator, the second output of the third resistor is connected to the first output of the alternating resistor, whose second terminal is connected to the second terminal of the fifth resistor, the average output is combined with the second terminal of the capacitor and the second terminal of the first resistor and is connected with a positive-polarity power supply bus, and the second terminals of the second, fourth, and sixth resistors are connected to a common bus. i 3. A comparator according to claim 1, characterized in that the power supply current driver is made on three transistors, two capacitors and seven resistors, the first terminal of the first resistor being the input of the current pulse generator, and connected to the first terminal of the capacitor, the second terminal of which is connected to the first conclusions of the second and the third resistors and the base of the first transistor, the emitter of which is connected to the emitters of the second and third transistors and with the first output of the fourth resistor, the collector — with the first terminal of the fifth resistor and the first terminal of the second capacitor, the second terminal of which is connected to the bases of the second and third transistors, and the first terminals of the sixth and seventh resistors; the collectors of the second and third transistors are respectively the first and second outputs of the pulse shaper R -L ABOUT n n / 7 I, J R the supply current, the second terminals of the second fifth and seventh resistors are connected to the common bus, the second terminal of the first resistor is connected to the supply voltage bus of a positive polarity, and the second terminals of the third, fourth and sixth resistors are connected to the power supply voltage of a negative polarity . ъ eleven WiS KZ V FIG. 2 FIG. 3 n, P U8x ( & / g. 4 K block 2  f I OtIloka.1 Figure 5 I