SU1566393A1 - Device for adaptive temporary discretization - Google Patents

Abstract

The invention relates to telemetry and can be used in cases where redundancy is required with a discrete presentation of the signal. The purpose of the invention is to improve the accuracy and noise immunity of the device. To do this, an analog-digital converter 4, a generator 5, two memory blocks 6, an address counter 8, a counter 12 for wok, a multiplexer 14, a divider 18, a block are entered into the device containing the converter 2, the errors of approximation, the key 1 and the comparison block 3. 19 comparisons, counter 20, elements AND 7, register 9, inverters 16, 21, element OR 10, delay element 11, differentiating element 17, triggers 13, 15, 22. This ensures the determination of the average activity of the recorded signal fragment and its transmission to the channel zi counts of the previous fragment with a frequency of its rational average activity, which improves the accuracy with non-stationary input signals and reduces the effect of interference on the choice of transmitted samples. 2 Il.

Description

FIG. Figure 1 shows the structural transformation dz that comes in.

device diagram for adaptive time sampling; in fig. 2 - timing diagrams for the operation of the device.

The device contains a key I, an approximation error converter 2 (PPA), a first comparison unit 3, an analog-to-digital converter k, a pulse generator 5, the first 6.1 and second 6.2 memory blocks, the first 7.1 and second 7.2 And elements, the first counter 8 of the address, register 9, the element OR 10, the element 11 delay, the third counter 12 of the wok, the third (counting)

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through elements AND 7 to the recording inputs of memory blocks 6.1 and 6.2. At the second inputs of the elements And 7-1 and 7-2 there are antiphase signals from the first and second outputs (O and non-Q) of the counting trigger 13, respectively, allowing and prohibiting recording. The positive edge of the pulse from the generator 5 sets the counter 8 of the address and the counter 20 to a new state, and after passing through the first inverter 16 and the differentiating element 17 (Fig. 2e) acts on the S input of the trigger 15 and sets

at its output signal 1, if on

The previous clock cycle of generator 5 was a significant countdown. Otherwise, the signal at the S-input of the trigger 15 confirms the presence of signal 1 at the output of the trigger 15 (Fig. 2e). Changing the state of the latter from 0 to 1 affects the input of the counter 12 of the order and transfers it to the new state.

The output code of the address counter 8 (Fig. 2g) affects the address inputs of the 6.1 and 6.2 memory blocks. After running by the counter 8, the address of all the states at the overflow output is set to signal 1 (Fig. 2h), which resets the counter 8 of the address to the initial zero state. At the same time, the overflow signal sets the counting trigger 13 to the opposite state, writes to register 9 a code from the output of counter 12 for the wok and resets the latter to the zero state after passing through delay element 11, and also enters through the element -OR 10 to the input of setting the zero of the counter 20. At the address inputs of multiplexer 1, signals Q (Fig. 2p) and non-Q (Fig. 2o) are received from trigger 13 which allow the output of the multiplexer to pass the code of that memory block 6c1 (6.2), which is written to during this period of operation counter 8 addresses is prohibited.

The code of the number of orders, determined for the period between the zero states of the address counter 8, arrives from the output of register 9 to the output of divider 18, in which the ratio of the maximum number of states of the counter of address 8 to the number of requisitions is located. The result of the division corresponds to the average interval between significant samples, measured in periods of the generator 5, and in the form of a code goes to block 19 of the code comparison. Block 19 also receives a code (Fig. 2) from the output of counter 20. which accumulates pulses from the generator 5o. The accumulation process occurs until block 19 of the code comparison does not generate an equality signal (Fig. 2k), which its output goes through the element OR 10 to the reset input of the counter 20 and the single-socket effect through the second inverter 21 (FIG. 2 l) to the S input of RS5663936

trigger 22, the output of which (Fig. 2 m) acts on the gate input of the multiplexer 1C, connected to its input the output of one of the 6.1 (6.2) memory blocks. The signal from the output of the differentiating element 17 (Fig. 2 d), acting on the R input of the RS flip-flop 22. sets the last to the initial state, which

corresponds to the closed multiplexer 1A, i.e. the time of presence of the output code at the output of multiplexer 1 does not exceed the duration

1 period generator 5.

The fragment length is determined by the frequency of the generator 5 and the capacity of the address counter 8. The frequency of the generator 5 is selected from the frequency properties of the signal and the permissible error of its representation.

The organization of a preliminary recording of the current fragment and its subsequent transmission with a frequency proportional not to instantaneous, but to the average signal activity in the analyzed interval, improves the accuracy of presenting a wide class of signals as discrete samples and reduces

30 The effect of interference on this view.

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Claims (1)

Invention Formula A device for adaptive time sampling, containing an approximation error converter, the first input of which is combined with the first key input and an information input of the device; the output of the approximation error converter is connected to the first input of the first comparator unit, the second input of which is the master input of the device; with the second input of the approximation error converter, characterized in that, in order to increase the accuracy and noise immunity of the device, Analog-to-digital converter, a second comparison block, counters, memory blocks, register, triggers, multiplexer, AND elements, OR element, inverters, divider, differentiating element, delay element and pulse generator, the output of which is connected directly to the first inputs of the first and the second counters and the analog-to-digital converter, and afterwards, Modiyt,