SU1179276A1 - Device for monitoring parameters - Google Patents

Abstract

A DEVICE FOR MONITORING PARAMETERS, containing a group of the first AND elements connected by the first inputs to the corresponding information inputs of the device, and the outputs to the information inputs of the first register associated with the output of the last bit with the first output of the device and with the information input of the second register synchronizing input - with the output of the second element And connected by the first input to the clock input of the device, a pulse counter connected by the output to the zero input of the trigger connected by the direct output to the second With the device output, the first element is NOT, the third element is AND, characterized in that, in order to increase the speed of the device, the element OR is entered into it, the second element is NOT, the group of EXCLUSIVE OR elements connected by the first inputs to the corresponding outputs of the first register, the second inputs to the corresponding outputs of the second register, and outputs to the inputs of the OR element connected by the output through the first element NOT to the zeroing input of the first register and to the single input of the trigger connected by the inverse output to the second input The first AND elements to the first input of the third AND element connected by the second input are with the clock input of the device, and the output is I with the zero input of the pulse counter and through the second element NOT to synchronization (the trigger input of the second register and the pulse counter is connected to the output of the second element I, which is connected by a second input to the direct output of the trigger. Is5 O)

Description

The invention relates to automatic storage, computing and telemechanics and can be used in processing information about the state of objects.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 - time diagram of his work.

The device contains information inputs li-1, block 2 of the first elements AND 3i-3n, first register 4, consisting of flip-flops 5 | -5l, second output 6 of the device, second register 7, block 8 elements EXCLUSIVE OR 9i-9, the element OR 10, the second element is NOT 11, the trigger 12, the first element is NOT 13, the pulse counter 14, the second element is AND 15, the third element is AND 16, the clock input 17 of the device, the first output 18 of the device.

FIG. 2 digits indicate the change of signals at the corresponding outputs (inputs) of the device elements. This diagram shows the information signal only from the first sensor, and the change in the states of the bits of the first and second registers is shown only at the outputs of four bits of these registers (for the case of servicing four sensors).

The device works as follows.

In the initial state, registers 4 and 7, trigger 12 and counter 14 are in the zero state. At the device input 17, clock pulses are periodically received, which, through the elements AND 16 and HE 11, confirm the zero state of the counter 14 and the trigger 12.

At the output of the element HE 13, in the initial state there is a single signal, and at the other inputs and outputs of the elements there are zero signals.

When the information signal from the first sensor to the input b of the device arrives, the first element I 3 | block 2. At the output of this element, a single signal appears that acts on the single input of the trigger 5i of register 4, as a result of which the zero signal at its output changes to a single one. This signal arrives at the first input of the first element EXCLUSIVE OR 9i of block 8, to another input of which the zero signal acts at that time from the corresponding output of the second register 7. As a result, the output of the EXCLUSIVE OR element 9 | a single signal is formed, which through the element OR 10 is fed to the input of the element HE 13 and to the information input of the trigger 12. At the output of the element NOT 13 the single signal changes to zero, and after the end of the corresponding clock pulse, the trigger 12 switches to the single state. At the unit output of the latter, a single signal is generated, which is switched to the first output 6 of the device in the form of a signal. "There is information for preparing the reception of information by an external device. This signal also arrives at the second input of the AND element 15 to enable the passage of clock pulses through it. At the zero output of the trigger 12, the single signal changes to zero, resulting in the AND element 3 of the block 2 returning to the initial state (blocking the passage of input signals and blocking the passage of clock pulses through the element 16). From this point in time the clock pulses from the bus 17, the devices begin to pass through the AND element 15 to the synchronization (C) inputs of the counter 14, registers 4 and 7. As a result, the position code is successively promoted along the bits 5 of the first register 4 and switched Going to the second output 18 of the device while simultaneously recording this information into the second register (see Fig. 2). After zeroing the first bit 5i of register 4 at the output of the EXCLUSIVE or 9i element, the single signal changes to zero, but despite this, the output of the element OR 10, a single signal is maintained due to the sequential occurrence of these signals at the outputs of elements 92 ... 94 (these signals are not shown in Fig. 2).

Counter 14 counts the number of clock pulses that is necessary to read information from the first register 4. In this case (to service four sensors), counter 14 is triggered after four clock pulses passed through the first And 15 element. The single signal generated at the output of the counter 14 resets the trigger 12 to the zero state. At the end of the fourth clock pulse acting on the output of the element 15, a single signal from the first sensor is recorded in the first bit 7i of register 7 (see Fig. 2). This completes the polling and monitoring cycle of the object state sensors. Thus, information processing is performed during one cycle using a single series of clock pulses. Issuing information about the state of objects is produced in the form of a positional code. In this case, this code looks like 0001, which corresponds to the availability of information only from the first sensor. The cycle time of this device will be (and, where n is the number of sensors; ("is the period of the reading (clock) pulses).

If, after the end of the cycle of outputting information to the outputs of the device, the input information has not changed, then element 3 again triggers and the trigger 5i of the first register 4. As a result, as can be seen from FIG. 2, identical signals will act on all inputs of the EXCLUSIVE OR 9i elements, which will lead to a change in the single signal to zero at the output of the OR 10 element.

The next clock pulse, having passed the AND 16 element, will reset the counter 14 to the zero state and confirm the zero state of trigger 12. Thus, if the information has not changed to the next entry cycle, the device does not switch it to its outputs.

In the event of a change in the input information, this device produces the output of this information to its outputs as follows.

If a signal is removed from the first sensor in the absence of single signals from other sensors, then at the output of the And 3i element and the single input of the trigger 5i of the register 4, the single signal will change to zero. Since a single signal from the output of the element NO 13 acts on the zero input of this trigger, the flip-flop 5i of register 4 is reset to the zero state, after which the first signal of the EXCLUSIVE OR 9i element changes to a single signal. Due to the non-identity of the input signals, a single signal is formed at the output of this element, which through the element OR 10 is fed to the information input of the trigger 12. The latter switches to the single state at the end of the clock pulse. After that, the control signal “Is

information, and its output 18 is code 0000, which indicates the disappearance of the monitored parameter from the first sensor. The bits of the second register 7 successively 5 are zeroed by the clock pulses acting on the output of the AND element 15.

When saving a single signal from the first sensor and the arrival of, for example, a single signal from the fourth sensor, the device operates in the same way. Code 1001 is switched to the device output 18, indicating that the information from the first sensor is saved and the information from the sensor appears.

Thus, the device requires

j sensor service only one cycle

information processing and one phase clock

impulses while maintaining all functions

prototype.

The use of the device improves the speed by eliminating two idle cycles, one working cycle and using only one cycle in it to interrogate the states of the sensors and transmit the results of the interrogation as a sequential positional code to one of the outputs of the device. Win in speed4p-T

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Claims (1)

DEVICE FOR CONTROL OF PARAMETERS, containing a group of first AND elements connected by first inputs to the corresponding information inputs of the device, and outputs to information inputs of the first register, connected by the output of the last digit With the first output of the device and with the information input of the second register, the synchronizing input - with the output of the second element And, connected by the first input to the clock input of the device, a pulse counter connected by the output to the zero input of the trigger, connected by a direct output to the second the output of the device, the first element is NOT, the third element is AND, characterized in that, in order to improve the performance of the device, an OR element is introduced into it, the second element is NOT, a group of EXCLUSIVE OR elements connected by the first inputs to the corresponding outputs of the first register, the second inputs to the corresponding outputs of the second register, and the outputs to the inputs of the OR element, connected by the output through the first element NOT to the input of zeroing the first register and to a single trigger input connected by an inverse output to the second inputs of the first elements And to the first input of the third element And, connected by the second input to the clock input of the device, and the output - and with the zero input of the pulse counter and through the second element NOT - with the synchronizing trigger input, and the synchronizing inputs of the second register and pulse counter are connected to the output of the second element And, connected by the second input to the direct output of the trigger. SU ,, .. 1179276