SU1562929A1 - Device for regeneration of functions - Google Patents

Abstract

This invention relates to automation and computing. The purpose of the invention is to expand the scope by reproducing the functions of two variables. The device for reproducing functions contains 1 clock pulse generator, two counters 2 and 13, decoder 3, switch 4, a group of four multipliers 5, three formers 6–8 additional codes, four multiplexers 9–12, four converters 14–17 codes, adder 18, a memory block 19 of transform coefficients, three delay elements 20-22, and a group of elements AND 25. The principle of operation of the device is based on the interpolation of reproduced functions by Hermitian cubic splines. The use of additional multiplexers, code converters and additional code drivers allows reproducing the functions of one or two variables, which expands the field of application of the device. 1 il. 4 tab.

Description

The invention relates to automation and computing and can be used to calculate Hermitian cubic splines of two variables

Sjj. (U, V)

 i

 J

Yas (, E 0

Xv 3- (i)

Mr. De u, V

O / - spline coefficients;

 normalized argument value, U, V, 1; the number of subintervals of the function representation, according to sign 15629294

formations, elements 20 - 22 delays, reset buttons 23 and 24, a group of elements And 25. As a source

The codes of the nodal values of the interpolating coefficients can be used by a group of 26 memory registers.

Converters 14-17 codes provide the formation of pairs of values

10 (U, V) (1-UV), (U, 1-V), (1-U, 1-V), respectively, according to the code generated by the second counter 13. For example, with the number of recovery points of the function n in the interpolation region P

In the case of interpolating co) 5 W, the transducer codes must be the coefficients f; ; and about “all the way”; ,

1 - given as

 j codes in nodes uniform

the two-dimensional L-20 grid is triggered by the output corresponding to the satisfying interpolation conditions

) r s S (U, -sV.) f (, r; S r ,, l;

  „J i ,, iQ,

(2) 25

In Table 2 {a 0, a ,, and Z is the code at the control inputs of the multiplexer; A fe, At1, An, B10, B, B YL codes on the second and first inputs of multiplexers; Yfo, Y, Y p - codes at the outputs of 30 multiplexers (codes B are binary additions of codes A). Switch 4 provides the implementation of the table.3 switching

35

where Dr s is the order derivative (r, S).

The aim of the invention is to expand the field of application of the device by reproducing the functions of the two variables.

The drawing shows a block diagram of a device for reproducing functions.

The device for reproducing functions contains a generator of 1 clock pulses, the first counter 2, a decoder 3, switch 4, a group of four multipliers 5, shapers 6-8 additional code, multiplex van on the reproduction of function S on ry 9-12, second counter 13 , the precurrent (isj) -M segment of 9 points, the creators of 14 17 codes, the adder (U, V) € (0,1) using the expression 18, block 19 of the memory of the coefficients of the preceding

In Table 3 {a0, a1, aaj- code at the control inputs of switch 4; Y ,,, Y, y3, y. - codes on the corresponding (switch outputs 4.

The principle of operation of the device is basic

where G ,, Cr, ...,

formations associated with the current values of the arguments U, V expressions of the form:

1, (1-U) 2 (1-V) 2 (1 + 2U) (1 + 2V);

0-U) 1 ()) V; r5 (I-U) i (l-V) 2U (l + 2V);

Allocate the switchings listed in Table 1, taking into account the fact that (and KYY1;

 ; K ,, 1, p-1).

In Table 1, Y, n 0, ... 15 of the corresponding bit of the converter.

Multiplexers 10 - 12 provide the implementation of the table.2 switching.

In Table 2 {a 0, a ,, and Z is the code at the control inputs of the multiplexer; A fe, At1, An, B10, B, B YL codes on the second and first inputs of multiplexers; Yfo, Y, Y p - codes at the outputs of the multiplexers (codes B are binary additions of codes A). Switch 4 provides the implementation of the table.3 switching

van on the reproduction of the function S on the current (isj) -M segment of 9 points (U, V) € (0,1) using the expression

In Table 3 {a0, a1, aaj- code at the control inputs of switch 4; Y ,,, Y, y3, y. - codes on the corresponding (switch outputs 4.

The principle of operation of the device is basic

(1-V) 1 (3-2U) (1 + 2V); U1 (1-V) 1 (3-2U) V;

(l-V) i (U -) (H-2V);

.U2 (1-V) 1 (

(four)

G., (i-u) (l + 2U) (3-2V);

, 0 (l-U) av4l + 2U) (V-l);

, (1-U) V2U (3-2V);

2U (1-U) 47 (V-1) U;

(3-2U) (3-2V);

“,, (3-2U) (V-);

(U-l) (3-2V);

(1-U) (1-V).

Since on each (i, j) -M of the progress of the function (U, V)

then for t, g, ..., i1 (the relations are true

 sixteen

4 (U, V) (l-U, V); “M, U, V) .I-V);

(five)

jmtM (U, V) Ksflm (l-U, l-V);

, 2,3,4 and the values of K - ,, Kg, K 3 are given in table 4

Therefore, to reproduce at each (i, j) -M segment of interpolation the intermediate values of the function at the points,, 2-n- ..., K -1, ..., V 0, pi, 2n-1,. ., 1n-1,. .., I, (where K, 1 are integers), the values of the transformation coefficients вычис., (U, V) Oa (U, V), (U, V), S4 (U, V) which are stored in memory block 19.

The group of registers 26 stores the values of the interpolated function f; ;

 Mr. J

and its derivatives f Vjj 5 f Vj Reproduction of the function S is carried out in four cycles. In the first cycle, the value is calculated.

+ uh

C1 (U, V) f, .jj + C, (U, V) f (.11 +

(u, v) + t: 4 (u, v) f (: j1

on the second

(0.1)

St Cs (U, V) ffMij + (U, V) f VT / .j +

+ 7 (u v fV ;; j + vu.vyf.

and partial amount

S on the third

eleven

St + S ,,

(m;

s3 VD.v) fb | Vl + Vu, v) f7;, +

+ ". Ј, ;;; + s (u, v)

and partial amount

113

 S t4 + S3,

1562929

on the fourth

four

)

. (0.11

s V.v..j +. + f "(u, v) f, -; M-t, +

H + 13 (U V) f С-1 ° 1 + J CU V) f (UI

J Sf i + 1, JH f6 u -1-1 t. jn

(Ii)

and the final value of the function at the point (U, V) in the area (i, j)

, pS, I 2 3 + S1

10 where u is. ; m

V In 1, U2;

K, 1 0,1, ..., p-1.

The device works in the following 15 ways.

At the beginning, the buttons 23 and 24 zero the counters and the adder. At each segment bounded by f (.,

fi, 5 f iVt, j. ff + i, jf, the calculation of 20 spline values is performed in four clocks. In the first clock cycle, switch 4 issues the values f-, f f:,

(1.01 jr 0.111 (J -J

f

well multiplexers 10-12

J miss their direct codes for the first

25 inputs of group multipliers 5, to the second inputs of which from the memory block 19 through the decoder 3, the counter 13, the code converter 14 and the multiplexer 9 are given the codes Ј., (K, 1), Oa (K, 1),

30 SE (K, 1) (K, 1), corresponding to the K, 1 codes, formed by the counter 13. The multipliers of group 5 calculate the corresponding products, and on the adder 18, the signal from element 21

This delay is calculated by S value according to expression (6). Further calculations are performed similarly and partial accumulators are accumulated on the adder 18 in the respective calculation steps.

40 sums S 1g, S 1:23, S, according to expressions (8), (10), (12). The fourth clock pulse zeroed the counter 2, and the value of the function S comes from the output of the group of elements AND 25 to the output of the device. The counter code 13 is incremented by one and the calculations are performed at the next point.

(eight)

(9)

ten)

Claims (1)

Claim 50 A device for reproducing functions, comprising a clock pulse generator, connected by an output to a counting input of a first counter, outputs of which bits are connected to inputs of a decoder connected by outputs to control inputs of a first multiplexer, a second counter, a group of four multipliers connected by outputs to informational 715 the inputs of the adder, the memory block of the conversion factors and the switch, the information inputs of which are connected to the input buses of the node values of the interpolating coefficients of the device, and the first output - to the input of the first multiplier of the first multiplier group, characterized in that reproduction of functions of two variables; three additional codes are added to it, second to fourth multiplexers, four code converters, three elements per supports and a group of elements And, the input of the first factor of each j-ro multiplier group (1 j Ј b) is connected to the output of the J-ro multiplexer connected by the first information input to the output of the (jl) -ro driver of the additional code connected by the input to the j- switch output and the second information input of the j-ro multiplexer, and the inputs of the second factors of all multipliers of the group are connected to the corresponding eight corresponding code outputs of the memory of the conversion coefficients connected by the address input to the output of the first multiplexer connected from the first to the fourth in. formation inputs with the outputs of the corresponding code converters, the bit inputs of which are connected to the bit outputs of the second counter connected by a counting input through the first delay element to the high bit output of the decoder, and the output of the clock generator is connected via a second delay element to the clock input of the adder connected the zeroing input with the output of the third delay element, the input of which is connected to the output of the first delay element and the first input of the AND group, connected in orymi inputs to the outputs of bit adder rows, and output - with output device, wherein the outputs of the first schatchika bits connected to the control inputs of the switch and the control inputs to the second to fourth multiplexer h. Table 1 ar ...... 1562929JO Table 3 Table 4