SU1559418A1 - Clock synchronization device - Google Patents

Abstract

The invention can be used in automatic frequency control devices to ensure synchronism of the receiving and transmitting parts of the equipment for transmitting discrete information. The purpose of the invention is to improve the synchronization accuracy by eliminating the sequence (alternation) of clock pulses at the output of the device in the event of a phase mismatch. To do this, a clock synchronization device containing a master oscillator 1, a divider 2 frequencies, a block 3 for selecting clock pulses, an RS flip-flop 4 and an AND 5 element are entered for the AND 6, OR 7 and D-flip-flop 8. 1 Il.

Description

one

(21) 4396123 / 24-09

(22) 03/21/88

(46) 04.23.90. Bul 15 (75) I.M. Zemlnoi

(53) 621.394.662 (088.8),

(56) USSR Author's Certificate No. 788409, cl. H 04 L 7/02, 1979.

USSR Author's Certificate No. 788411, cl. H 04 L 7/04, 1979,

(54) DEVICE OF CLOCK SYNCHRONIZATION

(57) The invention can be used in automatic frequency control devices to provide

synchronization of the receiving and transmitting parts of the equipment for transmitting discrete information. The purpose of the invention is to improve the synchronization accuracy by eliminating the sequence (alternation) of clock pulses at the output of the device in the event of a phase mismatch. To do this, a clock synchronization device containing a master oscillator 1, a divider 2 frequencies, a block 3 for selecting clock pulses, an RS flip-flop 4 and an AND 5 element are entered for the AND 6, OR 7 and D-flip-flop 8. 1 Il.

V

with

The invention relates to a technique for transmitting discrete information and can be used in automatic frequency control devices to ensure synchronism of the receiving and transmitting parts of the equipment for transmitting discrete information.

The purpose of the invention is to improve the synchronization accuracy by eliminating the violation of the sequence of clock pulses.

The drawing shows a functional electrical circuit of a clock synchronization device.

The device contains a master oscillator 1, a divider 2 frequencies, a block 3 of the selection of clock pulses, RS-flip-flop 4, the first element And 5, the second element And 6, the element OR 7 and D-flip-flop 8.

The device works as follows.

The pulses generated by master oscillator 1, arriving at the counting input of the divider 2 frequency, cause the output of the block 3 of the selection of clock pulses with a tracking frequency equal to the tracking frequency of the input clock pulses input to the device FT "Sign of the device synchronism is a situation when the FT pulses and the pulses at the output of the sync pulse block 3 appear simultaneously. In this case, the FT pulses arriving at the input of the device synchronously (with an accuracy of one period of the frequency of the master oscillator 1) with the formation of a pulse at the output of the sync pulse allocation unit 3 do not cause a change in their alternation.

If the input clock pulse arrives at the FT input of the device before the next pulse is formed at the output of the sync pulse selection unit 3, then this pulse arriving at the input Setting 1 RS-trigger 4 allows the next pulse frequency of the master oscillator 1 to pass through the first AND 5 element Since the D-flip-flop 8 is in the zero state, a frequency divider 2 at the input of the single-state setting, at which the clock extracting unit 3 generates a pulse. The impulse installation from the output of the first element And 5 also comes

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five

0

five

0

five

to the second input of the OR element 7 and further to the input of the RS-flip-flop 4, set it to the zero state, and keeps the D-trigger 8 in the zero state after the positive edge of the pulse from the output of the sync pulse 3 to the clock input.

If the pulse at the output of the sync pulse selection unit 3 is generated before the input clock pulse arrives at the input. The FT device then enters the clock input of the D-flip-flop 8, it sets it to one. The input clock pulse arriving at the device input sets the RS-flip-flop A to one and thereby permits the passage of the frequency pulse of the master oscillator 1 through the second element And 6 to the input of setting the zero state of divider 2 frequency and to the first input of the element OR 7, setting the triggers 4 and 8 to zero. As a result, the state of the divider 2 frequency and its frequency is zero and the phase difference is eliminated with an accuracy not exceeding the period of the frequency of the master oscillator 1.

Thus, the use of the proposed device eliminates the violation of alternation of clock pulses at the output of the device in the event of a phase mismatch.

Claims (1)

Invention Formula A clock synchronization device containing serially connected master oscillator, frequency divider and clock extractor, as well as serially connected RS flip-flop and the first AND element, characterized in that, in order to improve synchronization accuracy by eliminating the sequence of synchro pulses, D-flip-flop, the OR element and the second AND element, the output of which is connected to the input of the Setup 0 frequency divider and the first input of the OR element, the output of which is connected to the inputs of the Installation 0 D-tr igger and rs flip-flop, the input of which I is the information input of the device, the rs flip-flop output 515594186 connected to the inverse information OR, and to the input Installation 1 with the D-flip-flop trigger and the first frequency input, and the output of the block the second element And, the second input of which the selection of clock pulses is connected pogo connected to the second input of the first. with the clock input of the D-flip-flop, output And the output element of the master. Which is connected to the third inverse generator, and the output of the first element input of the first element And and the third Ta And is connected to the second input element-input of the second element I.