SU1552169A1 - Device for recognition of boolean function linearity - Google Patents

Abstract

The invention relates to digital computing and can be used for hardware support of computations in complexes of computer-aided design of discrete devices, image processing, data compression, in systems for the synthesis of LSI topology and VLSI. The aim of the invention is to enhance the functionality by recognizing the linearity of the Boolean functions defined in a generalized arithmetic polynomial form. This goal is achieved in that the device comprises a switch 1, a block 2 of registers, a computing block 3 and a block 4 of control. 6 ill., 1 tab.

Description

V

(L

I

one

sd

ate

O5

with

Output

fi, 1

The invention relates to digital computing and can be used for hardware support of computations in complexes, automated design of discrete devices, image processing, data compression, in systems for the synthesis of LSI and VLSI topologies.

The aim of the invention is to expand functional capabilities by recognizing the linearity of Boolean functions defined in a generalized arithmetic polynomial form.

FIG. 1 shows a diagram of the device; FIG. 2 - switch diagram; in fig. 3 functional layout of the multiplexer node; in fig. h is a block register scheme; in fig. 5 diagram of the computing unit; in fig. 6 is a control block diagram.

The device contains a switch 1, a block 2 of registers, a computing block 3 and a block k of control. Switch 1 contains - .1 nodes of 5 multiplexers, where n is the number of variable Boolean functions. Registers block 2 contains 2P registers 6 Computational block; approx 3 contains 2P subtracters 7 2 - 1 comparison elements 8 and element 9. The control unit A contains a generator 10 clock pulses, an element 11. A AND element 12, an estimator 13 - decoder 1 and trigger

nineteen,

Arithmetic polynomial form; | the Boolean function f (x) has the following form:

P (x) P0 + Pfxn + p2x ,, t +

+. . -fPnn.j X 4 HP

2 "-i.

chg- i ch p-1 and / 1

And pixi x hch 0

where p; 6z (i 0,2 - 1), Z - a set of integers such that the value of P (X), l on any set of variables,

X1 to Y.; - Ai

I ° & 1

L; I 1. X ...

1n-. in

n-bit binary

Representation code of the parameter i.

The arithmetic polynomial form P (X) of the Boolean function f (x) is

is a vector of coefficients P

 rv P ,,..., Pg «-1-OT, which is the result of performing a conjunctive transformation on a vector of values of X. x (0 x ... x J of the Boolean function f (x).

P KtnXi (

(2)

where is the conjunctive transformation matrix of dimension 2P х .п. formed by rule

K0 „K„, ® KeB.t,

(3)

where ® is the symbol of the Kronecker product.

The generalized arithmetic polynomial form already defines a system (tuple) of Boolean functions spatially ordered. This system is written as

Јпь. (Х)) ... f0,

If the j-th function of the tuple (j 0, t-1) is represented as an arithmetic polynomial form P; (x), then multiply by a weighting factor 24 and add the polynomials obtained with weights, then the result is a generalized arithmetic polynomial form D (x), where

m-i

D (x) JT 2J R. (x)

2 -1

G °

d- x; x

pg y „-, Xn

The generalized arithmetic polynomial form of the system of Boolean functions D (x) is uniquely represented by the vector of coefficients D Јde, d t, ..., d 2.n, r.

The linear generalized arithmetic polynomial form of the system of Boolean functions fj (x) (j 0,, m-1) has the following form:

LD (x) 10 + 1, xp + 14 xpn +

P

+ ... + - 10 +. (5)

1 ™ 1

51552169

s (5) it is clear that the generalized arithne is not eligible for

The metric polynomial form is linear if it consists of only the terms defined by only one Boolean variable x; (i 1, p).

Thus, if the coefficients of the generalized arithmetic polynomial form P (x) satisfy the condition

WITH

d; Oh for i jЈ 2, CO 0, p-1, i -0 ,,

This generalized arithmetic polynomial form of the system of Boolean functions is linear.

The linear generalized arithmetic polynomial form of the system of Boolean functions is uniquely determined by the vector of coefficients LD 10, 1 ,, ..., 1 "3T. A characteristic feature is that this vector of coefficients contains only n + 1 elements, while the vector of coefficients is not equal ol - xw х (г1 - х ™ - х (-хЫ х (0) - xul - х (41 - х (б1

 x (n

   - L

Xyu1. X (2P x (

Computing unit 3 operates as follows. The elements of the vector of Chl values (x (o1, ..., enter the inputs of the subtractors 7. In which the values of the difference of the incoming elements x 2 - x are formed. From the outputs of the calculators 7i:

fi -and (f2)

the values of the differences xy - x are transmitted to the inputs of the comparison elements 8 and 8j, from the output of which the equal value of the operands at the inputs (high logic level) is fed to the input of the element 9, the output of which forms a high logic level in the case of high logic levels all its inputs. The decoder 14 is designed to generate signals at its outputs in accordance with the table.

The control unit k operates as follows. At time t, a high logical level of voltage is fed to the trigger input of the gene

- The linear generalized arithmetic polynomial form contains 2 elements. This property determines the feasibility of using a linear generalized arithmetic polynomial form, which allows reducing the amount of computation during processing and the amount of memory when storing vector vectors of coefficients. Thus, it becomes necessary to recognize the linearity of generalized arithmetic polynomial forms defined by their vectors of values X ,.

15 For a generalized arithmetic polynomial form of a system of Boolean functions, there is a one-to-one correspondence between the vector of X values and the coefficient vector D,

20 on expression expression

about k2 „.хв.

(7)

From (7) it follows that in the general case 25 the condition of linearity of a generalized arithmetic polynomial form is

(-XY

()

 x (. x (j

   - LA

- x

()

(eight)

ratora 10 clock pulses, as well as the first input of the counter 13, in which the number 2 - n is written, the code of this number from the outputs of the counter

13 enters the inputs of the decoder 14, at the outputs of which low logic levels of voltage are formed in accordance with the table.

At the moment of time tz, at the output of the generator 10 a clock pulse is generated, coming through the element 11 at the second input of the counter 13. The counter 13 goes to state 2 - n + +1, the code from the outputs of the counter 13 goes to the inputs of the decoder 14, you

the moves of which are formed signals in accordance with the table.

At times t4 and ts, the operation of the control unit 4 occurs in the same way as at tj, only the counter 13 goes to the state 2k-n + 2n2k-n + 3, respectively.

At the moment of time tg, the counter 13, when the tactical section of its second entrance appears in me Co 2

the second pulse goes from state 2k - 1 to state 0, and from its output the overflow signal is fed to the inputs of the AND-HE element 12 and the trigger 15-. which goes from zero to one state. From the output of the NAND 12 element, the voltage front signal from the Low logic level to the high is input to the generator stop input of 10 clock pulses.

Consider the operation of the device for the case of p. 4. The elements of the vector sign from the second output of control unit 4 are input to the record of block 2 of registers and synchronize the writing in its registers 6g- 64 of the values of x elements (41, xsgl, x (vector xo) the registers remain unchanged.

If x is executed (c - x x "0" ("l

15

, then the logic level of the voltage is kept high at the output of the computing unit 3, the counter 13 goes from the state 110 to the state 111.

post-1E At the moment of time te, the clock pulse arrives at the counting input of counter 13; which then goes from state 111 to state 000 and generates an overflow signal. The overflow signal enters the input of the trigger 15 and translates it into a single state, and also enters the input of the element AND-NO 12 and further

He x (0. x “5) are fed to the information inputs of the first Device Group. After arriving at the input of the high logic level control block A mode (time point c) a number 13 is written to the counter 13, the code 100 corresponds to it, therefore, at the first output of the control block C, the zero signal is generated 25 at 8X ° D of the generator 10 tzk20

The cells are transmitted to the control input of the switch 1.

The clock pulse generated by the generator 10 (time t) is fed to the input of the record of registers 6 and synchronizes the writing to registers 6 elements of the vector of values X-p coming from the output of switch 1. Under the action of this clock pulse, the counter 13 changes from state 100 to state 101. If x-xm is being executed) 30

35

 XU1 x (7l XW

X W x (4)

x (X00)

 ) (K)

)

- x) - x UV |

then the output of the computing unit

3 remains high logic level,

At the moment of time c, a clock pulse from the second output of control unit 4 is transmitted to the input of the record of registers 6 and synchronizes the recording in them of the elements of the vector of values X,

40

45

D6)

. ((ABOUT)

x

Og) v (

x,), These values are written to registers 6p (p 2.8), the same registers are written to the remaining registers of block 2 registers.

Tov pulses.

Thus, the presence of a single state of the trigger 15 when the generator of 10 clock pulses is stopped indicates the linearity of the recognized generalized arithmetic polynomial form.

If the generalized arithmetic polynomial form is not linear, then at the recognition stage (for example, at time t) one of the equalities (7) does not hold. At the output of the computing unit 3, a low voltage level is formed, this signal is fed to the input of the mode of the control unit 4 and then to the input of the AND-NO element 12, from the output of which a high logical voltage level is transmitted to the input of the generator 10, Thus , the presence of a zero state of the trigger 15 when the generator of the 10 clock pulses is stopped indicates that the recognized generalized

information that was written in them-50 arithmetic polynomial form

At the exit

on at time tz. computing unit 3 remains a high logical level of voltage in the case of - x

 x (40 x (6) x (d) x (W) x H O - x 4. Under the action of the same clock pulse, counter 13 changes from state 101 to state 110.

At time t & clock them

The pulse from the second output of control block 4 is fed to the input of the record of block 2 of registers and synchronizes the recording in its registers 6r- 64 of the values of x elements (41, xsgl, x (vector xo). The contents of the remaining registers of block 2 of registers remain unchanged.

If x (c is x x 0n) ("l

, then the logic level of the voltage is kept high at the output of the computing unit 3, the counter 13 goes from the state 110 to the state 111.

0

five

0

five

Tov pulses.

Thus, the presence of a single state of the trigger 15 when the generator of 10 clock pulses is stopped indicates the linearity of the recognized generalized arithmetic polynomial form.

If the generalized arithmetic polynomial form is not linear, then at the recognition stage (for example, at time t) one of the equalities (7) does not hold. At the output of the computing unit 3, a low voltage level is formed, this signal is fed to the input of the mode of the control unit 4 and then to the input of the AND-NO element 12, from the output of which a high logical voltage level is transmitted to the input of the generator 10, Thus , the presence of a zero state of the trigger 15 when the generator of the 10 clock pulses is stopped indicates that the recognized generalized

to the class of linear.

Claims (1)

Invention Formula A device for recognizing linearity of Boolean functions, containing a switch, a computing unit and a control unit, characterized in that, in order to expand its functionality by recognizing linearity of Boolean functions specified in a generalized arithmetic polynomial form, it contains 2P registers (where n is the number of variable Boolean functions), and the inputs of the vector of values of the generalized arithmetic polynomial of the device are connected respectively to the information inputs of the first switch group, the outputs from the first to the 2nth of which are connected respectively to the information inputs M n-l I will give the registers from the first to the 2nd, and the outputs of the registers from the first to (2 -1) -th are connected respectively to the information inputs of the second group 00000000 11111111 11111111 % tl 552169. YU the switch and, respectively, to the information inputs of the first group of the computing unit, the outputs of registers 2p through 2nth are connected respectively to the information inputs of the second group of the computing unit, the output of which is connected to the mode input of the control unit, the first, second, and third outputs of which are connected respectively to the control input of the switch, to the write inputs of all registers and to the output of the linearity feature of a recognizable generalized arithmetic polynomial form of the device, the trigger input of which Keys to the trigger input of the control unit. . about . one . about . Editor V. Petrash Compiled by V. Smirnov Tehred L. Olsh shyk Proofreader E. Lonchakova Order 330 Circulation 5b1 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab., 5 Production and Publishing Combine Patent, Uzhgorod, Gagarin st., 101 Subscription