SU1550522A1 - Circular system for information exchange - Google Patents

Abstract

The invention relates to computer technology and data transmission systems, is designed to build local networks that provide information interaction of computing equipment: In flexible automated manufacturing systems / HAP, GAPS /

in systems of automated production management and technological processes

in institutional automation systems

in design automation systems / CAD /. The purpose of the invention is to increase the capacity of the system. The goal is achieved by the fact that in a ring system, each of the devices of which contains a receiver, a switch, a transmitter, two triggers, an information accumulator, a pulse distributor, a decoder, an OR element, a permanent memory, a control node, a block of communication registers with the subscriber , voltage control relay, a buffer transfer node was inserted into each device, including a shift register, two counters, two triggers, three AND elements, memory. 2 Cp f-ly. 10 Il. 2 table.

Description

The invention relates to computing technology and can be used as a local computer network, distributed design automation systems (CAD) and office automation with the use of personal professional electronic computers (PCED).

The purpose of the invention is to increase the capacity of the system.

FIG. 1 shows a block diagram of a device for transmitting and receiving system information; in fig. 2-4 - functional diagrams of information storage,

pulse distributor and information transfer unit; at aig. 5-8 are flowcharts of the generalized Functioning algorithm, the algorithm of the main work cycle, the modes of receiving and issuing packets; in fig. 9-10 - timing charts of the transmission buffer in the formation and transmission of the data packet.

The device contains a receiver 1, a switch 2, a transmitter 3, a buffer node (buffer) 4 transmissions (for forming data packets and transmitting them in a serial code), reception trigger 5, information storage 6, pulse distributor 7, descrambler 8, transmission trigger 9, element LI 10, permanent memory AND, control unit 12, unit 13 of communication registers with the subscriber, power supply voltage relay 14,

Information accumulator 6 (FIG. 2) contains a 15-bit counter, a shift register 16 (for converting a sequential code to a parallel one), an address counter 17, a HE element 18, a trigger 19, a element 20, bus drivers 21 and 22, OR elements 23 and 24, memory 25.

The pulse distributor 7 (Fig. 3) contains a clock generator 26, And 27 and 28s elements, counter 29, information exchange speed switch 30. The buffer node (buffer) 4 of the transmission (Fig. 4) consists of a shift register 31 (to convert a parallel code in serial), counter 32 bits of the And 33 element, trigger 34 (transmission enable), trigger 35 (enable recording of information in the transmission buffer), address counter 36, And 37 and 38 elements, memory 39 (for generating a packet).

Switch 2 consists of the elements And 40 and 41 and the element NO 42 FIG. I.

The device operates in two modes: packet transit mode and packet transfer mode. In both modes, all information coming from the communication channel (line) is always sent to the storage device 6.

Packet transit mode The device (station) is usually in transit mode and in this case acts as a repeater amplifier. At the same time, information passes through receiver 1 and transmitter 3, and simultaneously arrives at accumulator 6. Upon receiving the start of packet sign, trigger 5 signals this to node 12 by issuing an interrupt request, i.e. provides the ability to programmatically analyze what package comes from. lines. The address of the recipient station specified in the packet format analyzes this address to see if it matches its own. If the station's program determines that the incoming packet is addressed to it, it disconnects the transit through the station until the reception of the entire packet to drive 6 is over. When receiving the end-of-packet feature, the transit state is restored.

five

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five

0

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five

Messaging mode.

The essence of the station is that it does not transmit a message to the communication channel until its ring path is free, i.e. until the station completely passes the next packet. If the ojr of the subscriber connected to the station receives a data packet, the station checks the status of the ring channel for its occupancy by the passing transit packet. If the channel is free, the station turns off the transit state, after which the packet, ready for transmission, is transmitted to the communication channel. Upon completion of the packet transmission, an analysis of the state of accumulator 6 is performed. If during the transmission of the own packet to the ring, other packets were received from the communication channel, then they are analyzed and, if necessary, transmitted further to the channel in a similar way. After f release of accumulator 6, the station restores the transit state.

If a transit packet is transmitted through the station at the time of transmission, the station waits for its end marker and performs the actions described above.

This mode can be used to clean the network from packets with broken structure, since at the moment when such packets are found in the station's storage unit, the program can analyze their structure.

The combination of two modes — transit and transmission — allows the station program to send packets to a communication channel and receive addressed packets to it from the channel. The rules for exchanging information on the network and the packet formats are determined by the selected program algorithm.

An example is one of the implementations of the algorithm, applied in the version of the relay-03 station.

The format of the package includes the following gender: the address of the receiving station; the address of the sending station; packet length; data; check amount.

The maximum packet length depends on the selected buffer size in memory (256 bytes). In the present embodiment of the program, the maximum packet length is 1/3 of the buffer capacity.

The calculation of the checksum in this program implementation is based on the convolution modulo two, although

5155

you can use any other algorithm. The received station packet checks the correctness of the checksum and sends a receipt to the sender. Upon receipt of a confirming receipt, the sending station destroys a copy of the sent packet in its buffer. Otherwise, this packet is retransmitted. The number of retransmissions can be limited and in case of a repetition counter expiration, diagnostic information can be provided to the subscriber connected to the station.

The network functions include self-diagnosis procedures, which consist in the fact that diagnostic packages periodically circulate in the network. The purpose of the dressing is to monitor the integrity of the ring line, monitor the presence and condition of stations operating in the network.

The permanent (reprogrammable) memory (ROM) 11 and node 12 together constitute the control unit, which operates in accordance with the control program algorithm stored in the ROM 11, and the type of equipment of the subscriber (user) connected to the unit. 13; in particular, a UV erasable ROM (K573 series) and a K1810BM86, KM1810UM88 or 880D microprocessor can be used. The operative memory of the control unit uses the memory of the information storage with the capacity from 4 4K to 16 Kbytes, and the storage device 6 uses 256 bytes for its buffer.

Table 1

ten

Oh oh

I eat at the beginning of the buffer)

03 RAM selection

14 Resolution Transmission from the Transmission Buffer (RP)

05 Write to buffer

transmission (ZP)

16 Shutdown Transit (FROM)

07 Transit Authorization (RT)

18 Selection of ROM (with

device initialization)

For communication of node 12 with various units of the device, 16 bits of the SM data bus and control signals are used: ZPR1-ZPRZ interrupt requests 1-3, the assignment of ZPR1-ZPRZ signals is given in Table. 2; ZZH - request capture tires; RZH - permission to capture the tires.

25

35

i

table 2

As a block 13, an LSI controller of a serial or parallel interface (KP580 series) can be used, with which, depending on the particular scheme chosen, information can be exchanged with the subscriber.

From the address space of 1 MB of the microprocessor, in accordance with the specifics of its use in the device, the address space of 128 KB is used.

The address bus AO is used to select the low byte of data from the memory. The address buses A1-A13 address the ROM 11 and the memory 25, A14-A15 are used to select the ROM, the memory 25, and generate control commands in accordance with Table. one.

40

45

50

55

The procedure for direct memory access is used in the process of receiving information into the buffer storage device described | below.

When the supply voltage is applied to the device, the relay 14 is triggered and the communication line is connected to the input of receiver 1. When a start zero bit appears in the communication lines, a trigger 5 is set.

This signal is received from node 12 as a request for interruption of SRS1, informing the control program of the beginning of reception of a packet of information over a communication channel. Information from the output of the receiver, 1 also goes to switch 2.

Depending on the state of trigger 9, switch 2 transmits signals from receiver 1 output to transmitter 3 input (Transit mode) or transmission 4 output buffer to transmitter 3 input (Transmission mode).

Transmission buffer 4 (FIG ,, 4) is used to convert information from a parallel code to a serial one, generate a data packet and issue it to the transmitter input for further transmission to a ring (line).

Transmission buffer has two modes of operation: recording mode (packet formation) and transmission mode

Recording mode

The information from the subscriber, processed by the program (microprocessor) and intended for transmission to the line, goes byte-by-bye from the data bus to the shift register 31, where it is serialized. At the same time, but with the appearance of a 1-byte data bus, the decoder 8 generates an RFP signal, which writes the byte to the register. The shift of information (serialization) and its recording in the memory 39 of the transmission buffer is carried out by pulses of frequency F, which are generated

in the distributor 7. I

Timing diagrams for recording synchronization are shown in Fig. 9.

The signal of the decoder ZP is set to the Record trigger 35 mode. The inverted output of the trigger 35 receives the resolution of the input of the counter 32, which controls the number of bits of information recorded in memory 39.3 and resets the trigger 35 to its original recording state bytes of information. Same

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the signal accesses memory 39.

A direct recording trigger signal is generated from the direct output of the recording trigger, which permits the passage of recording synchronization pulses in the distributor 7, as well as the passage of recording pulses through Lemect I 37 to the memory mode selection input 39.

When the packet is formed, the counter 36 is sequentially incremented, thereby ensuring the recording of each bit of information received in the serial code from the output of the shift register 3 to the information input of the memory.

After the information byte has been recorded, the counter 32 generates a reset pulse, which causes the trigger 35 to return to its initial state.

Counter 36 is not reset; The first bit of the packet byte is written to the next address cell.

Writing data to the memory continues with increasing the address until a packet of the desired length is formed. The completion of the package formation is tracked by the program.

Transfer mode

When the need arises to issue information to the communication channel, an RP signal appears at the output of the decoder 8, which resets the transmission buffer counter 36, sets the trigger 34 to the Transmission mode, clears the DPR 3 interrupt request and enables memory access 39, and generates a signal RP (transmission permission).

After receiving the PM signal, buffer 4 functions independently of the program (microprocessor). The autonomy of the transmission buffer, i.e. the independence of the transmission rate from software synchronization allows for an increase in the speed of transmission to the line in comparison with the prototype.

The operation of the circuit (transmission buffer) in transmission mode is illustrated by the timing diagram of FIG. ten.

In the event that someone else’s station is not passing a packet or receiving a packet from a line, counter 36 and element 37, which controls the selection of the operating mode of memory 39s, receive transmission synchronization pulses (frequency F.).

At the output of the memory 39, the information (the formed packet) is read in a sequential code, which is transmitted to switch 2 and then to transmitter 3 to the line.

Counter 32 monitors the end of the packet during transmission. When a packet trailer appears at the memory output — two bytes of FF, a pulse appears at the output of the counter, which flushes trigger 34 and address 36.

The signal from the inverse output of the trigger 34 is an interrupt request request 3, which informs the microprocessor about the end of packet transmission.

The signal RP ceases to be active and prohibits in the distributor 7 the formation of transmission synchronization pulses (frequency F /).

Distributor 7 (Fig. 3) is designed to generate clocking signals for all nodes of the device, including the power supply for the clock input of the microprocessor. The quartz oscillator 26 has a direct and inverse output of the fundamental frequency F and F.

On elements 27 and 28, a scheme for generating a transmission buffer synchronization signal is implemented. The RF signal allows the passage of the pulses of the fundamental frequency F for synchronization of the recording during the formation of a packet in the 4th transmission buffer.

If a packet does not pass through the device (Transit mode), a packet is formed in the transmission buffer and a signal is received for transmission (Transit and Allow Dist. Signals are active), the output of the distributor 7 receives transmission synchronization pulses whose frequency (F2) is obtained by dividing the fundamental frequency (F) counter 28 and set by switch 30.

The same frequency (F.) synchronizes the reception of information from the line to the drive 6.

Information accumulator 6 (FIG. 2) is intended for receiving serial information from receiver 1, converting it into parallel form, writing to buffer zone of memory 25 at sequential addresses, and issuing an indication of the end of an information packet (signal End of packet). The buffer zone is 256 bytes of shared RAM 25. A series-parallel converter.

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P

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A register of 16, clocked from the distributor 7, is received. The reception of the next bit in the register 16 occurs in the middle of the bit duration, which ensures reliable reception during non-synchronous operation of the clock generators of the receiving and transmitting stations.

Counter 15, after receiving the last bit of a byte, generates a request for direct access to the EF memory and increments the address at the input of the counter 17. The enable signal of the direct access PZH returns the counter 15 to its initial state, opens the bus drivers 2 and 22, generates a sampling signal memory 25, which through the element OR 23 enters the input of the memory sample 25. The same signal through the element NOT 18 enters the input of the trigger 19, which generates a write enable signal, which through the element OR 24 enters the input resolution of the memory 2 five.

Claims (3)

1. Ring system for information exchange, containing M information transmitting and receiving devices, each of which contains a receiver, a switch, a transmitter, a pulse distributor, a drive, a decoder, a reception trigger, a transmission trigger, an OR element, a control node, a permanent memory block registers of communication with the subscriber, voltage control relay, the outputs of the transmitters of the i-th (i 1, M-1) and M-th devices for transmitting and receiving information of the system are connected respectively to the inputs of the receivers (i + l) -ro and the first transmission devices and receivers and information systems, each of which relays a control winding voltage power source connected to the poles of the power transmission device and reception yn system formations, relay contacts are connected to the receiver input and the Transmitter output, the receiver output is connected to the receive trigger input, the storage information input and the first switch information input, the control input of the switch connected to the output of the transmission trigger, inorma input output the control node is connected via the data bus to the information input-output of the accumulator, the output of the permanent memory and the information input-output of the block of communication registers with The input groups of the information and control bits of the inputs of which are the input-output of the device for connecting to the information and control input-output of the corresponding subscriber of the system, and the address input is connected to the address output of the control node, the address inputs of the accumulator, via the address bus, the fixed memory and the information r input of the decoder, the control input-output of the control node is connected via a control bus with the control inputs-outputs of the accumulator and the block of communication registers with the subscriber, by direct and inverse outputs the reception trigger control input of the decoder, a group of which the output is connected to the enabling input permanent memory, first and second inputs of the storage mode, the installation and the reset input transmission trigger output of the accumulator is connected to a reset input receiving a trigger inverse vhodom CONNECTION element, which is connected to the first input, characterized in that, in order to increase system capacity, a buffer transmission node is inserted into each system transmitting and receiving device, and the information input of the transmission buffer node is connected via a data bus to the information node control, and the first output is connected to the second information input of the switch, the recording and authorization inputs of the output of the transmission buffer node are connected to the group of outputs of the decoder, the clock input of the transmission buffer node dinene with the first output of the pulse distributor, the first and second resolution inputs of which are connected respectively to the second and third 0 five .Q 0 five the outputs of the transmission buffer node, the fourth output of which is connected via the control bus to the control input-output of the control node and the second input of the OR element, the output of which is connected to the fault input of the transfer trigger, the second output and the input of the pulse distributor mode are respectively connected to the clock input of the accumulator and the output transfer trigger. 2. A ring system according to claim 1, characterized in that the pulse distributor comprises a generator, a counter, two elements AND and a switch, the first input of the first element AND connected to the first input of the resolution of the pulse distributor, the second input of the first element AND connected to the output of the generator and the input of the counter, and the output is i the first output of the pulse distributor and is connected to the output of the second element AND, the first and second inputs of which are respectively the second enabling input and the input of the mode of the pulse distributor, g The group of outputs of the counter is connected through a switch to the third input of the second element I, and is the second output of the pulse distributor. 3. The ring system according to claim 2, in which the transfer buffer node contains a shift register, a bit counter, a memory, an address counter, two flip-flops, three AND elements, and the information input of the shift register is an information input of the transfer buffer node, the input the records and the clock input of the shift register are respectively the record input and the clock input of the transmission buffer node, and the output is connected to the information memory input, the output of which is connected to the first enable input of the bit counter and is the first output buffer The first transmission node, the output of whose issuance is connected to the first input of the first element AND and the installation input of the first trigger, the reset input of which is connected to the second input of the first element And and the first output of the bit counter, the counting input of which is connected to the clock input of the buffer node of the transmission, counting input the address counter and the first input of the second element And, the outputs of which are connected respectively with the address0 five 50 five memory inputs whose access input is connected to the output of the third element I, the second output of the bit counter is connected to the reset input of the second trigger, the setup input of which is connected to the write input of the transmit buffer node, and the forward output is the second output of the buffer node transmission and connected to the second input of the second element And, inverse the output of the second trigger is connected to the BTO eye, the resolution input of the bit counter and the first input of the third element I, the second input of which is connected to the fourth output of the transmission buffer node and the inverse output of the first trigger, the direct output of which is the third output of the transmission buffer node, the output of the first element I connected to the reset input of the address counter. Zg eleven 29 Allow Under, Transit Fig.Z Bp Sync block reyis / Lroy vCfojtf sa5on- 9 volume B 28 First n L H Training tables and workspaces one Setting hardware modes one Enable transit I Calculation own addresses Main loop -, x Exit on - - - - the center of feeds P Getting started on the power up FI.5 J Input from connected equipment Yes Formation of v / pts Bcsostmdettug You are 8c on connected but extradition, 6  RING Fie.7 Lllllal )P Sn Package 8 Forwarding transfer gear. Output Editor L. Pcholinsk Techred M. Didyk Order 274Discount 564Subscription VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow Zh-35, Raushsk nab 4/5 ishshshg d & SUIT Thebes. 9, Lie.I Proofreader. Ciple