SU1298760A1 - Information exchange system - Google Patents

Abstract

The invention relates to computing and can be used in distributed computing systems and computer networks of a ring structure. The aim of the invention is to increase the capacity of the system. The device contains information storage 6, receiver 1, transmitter 3, switch 2,. Register 4 shift. Receive trigger 5 and transmission trigger 9, pulse distributor 7 and decoder 8. In each information transmitting and receiving device, control unit 12 is entered, memory 11 is permanently connected, subscriber communication registers unit 13, OR element 10 and voltage control relay 14 nutrition 2 hp f-ly, 10 sludge, 2 tab. oh from 00 oi o

Description

The invention relates to computer technology and data transmission systems, in particular, to systems that interface a variety of electronic computers (COMPUTERS) and peripheral devices, control computing systems, process controllers, numerical control devices in flexible production systems (GPS). , as well as the construction of distributed systems for the automation of design and automation of institutional activity.

The purpose of the invention is the expansion of the pro-15 per packet coming from the line. According to the set-capacity of the system. In the format of the packet, the address stanna in FIG. 1 shows a block diagram of a device for transmitting and receiving information of the system of FIG. 2 and 3 — the recipient function analyzes this address to see if it matches its own. If the program determines that the incoming packet of the controller and the pulse distributor; on resovan her, she disables the transit of FIG. 4-6 are the timing diagrams of the operation of the device for transmitting and receiving information in FIG. 7-10 - block diagrams

The generalized algorithm of the function-25 transit is restored. nor, the algorithms of the main cycle of the ra- Message transfer mode. bots, modes of reception and issuance of packages through the station to :; the end of the reception of the entire packet in the drive 6. When you receive the sign of the end of the packet state

froB.

The device (Fig. 1) contains, whenI, that the station does not transmit a message to the communication channel until its ring path is free, i.e. Until the next 35 package passes completely through the station. If a data packet is received from a subscriber connected to the station, the station checks the status of the ring channel. The message transmission mode in this device is fundamentally different from the similar mode in networks with a contention method. The essence of the difference is the gateway 1, junction, softer 2, the transmitter reads in volume 3, shift register 4 (for converting the parallel code to serial), reception trigger 5, information storage device 6, pulse distributor 7, decoder 8, transmission trigger 9, element 1, 10, fixed memory (ROM) 11, control unit 12, unit 13 of communication registers with the subscriber, the subject of his occupation of the pass P .... .. 0 Shchim transit1Sh1m package. If the channel

is free, the station turns off the transit state, after which the packet, ready for transmission, transmits ... ,,,, .0 s to the link. Upon completion of the Pechik 17 addresses, the element is NOT 18, the trigger

. - This package is analyzed.

1U, element I 20, tire formers, „

 "", ", ;;. . states of accumulator 6. If at levels 21 and 22, elements OR 23 and 24, memory 25.

The distributor 7 pulses (fig.Z)

„„, Other packages, they are analyzed

contains a clock generator 26, count - cg, -, "r" t, -.,. 50 And, if necessary, are transmitted further

Chiki 27-29, element NOT 30, elements

OR 31 and 32, trigger 33.

 Switch 2 consists of elements And 34 and 35 and the element 36 (Fig. 1).

The device operates in two modes: packet transit mode and packet transfer mode. In both modes, all information coming from the channel

The information storage device (FIG. 2) contains a 15-bit counter, the shift register 16 (for converting a serial code into a parallel one), the transmission bursts to the ring of its own packet from the channel were received

into the channel in a similar way. After the accumulator 6 is released, the station restores the transit state.

If, at the time of the transmission, a transit packet is transmitted through the station, the doji station is taken to its end marker and produces the described actions.

(lines) connection, always sent to the drive 6 information.

Packet transit mode

The device (station) is usually in transit mode and in this case acts as a repeater amplifier. At the same time, information passes through receiver 1 and transmitter 3 and enters storage device 6. Upon receiving the sign of the start of a packet, trigger 5 signals this to node 12 by issuing an interruption request, i.e. provides the ability to programmatically analyze what

recipient information, the address is analyzed to match its own address. If the station program determines that the incoming packet is addressed to it, it disables the transit

transit recover. Messaging mode.

through the station to :; the end of the reception of the entire packet in the drive 6. When you receive the sign of the end of the packet state

I, that the station does not transmit the message to the communication channel until its ring path is free, i.e. until the next packet passes completely through the station. If a data packet is received from the subscriber connected to the station, the station checks the status of the ring channel. The message transmission mode in this device is fundamentally different from the similar mode in networks with the contention method. The essence of the difference lies in the subject of his occupation of the passage of the state of accumulator 6. If

m transfer to the ring own packet from the channel ev zi be accepted

into the channel in a similar way. After the accumulator 6 is released, the station restores the transit state.

If, at the time of transmission, a transit packet is transmitted through the station, the doji station is taken to its end marker and produces the actions described above.

This mode can be used to clean the network from packets with a broken structure, since at the moment when such packets are located in the station storage unit, the program can analyze their structure.

The combination of two modes — transit and transmission — allows the station program to pull packets into a communication channel and receive packets addressed to it from a channel. The network information exchange rules and packet formats are determined by the selected program algorithm.

(K573 series) and a microprocessor of the U880D or K1810BM86 type. As the block 13, the LSI of the serial receiving-transmitting device KR580BB51A is used, with which the output to the C2 and IRPS interface is realized. The operating memory of the control unit uses the information storage memory 25, for example, 4k-byte, and the storage device 6 uses its buffer 256 bytes. The address space of 64k bytes is used by the microprocessor in accordance with the specifics of its use in devices. For example, one of the implementations of the algorithm used in video can serve as an example. Address tires from AO to A11 address - ante relay station. In the format of the ROM 11 and the memory 25, A12 the following fields are not provided: use, A13-A15 are used for the address of the station recipient J the address of the station sampling memory 25 and the generation of the sending command J the packet length J data-.

20

the ones; check amount.

The maximum packet length depends on the selected buffer size in memory 25. In the current version of the program, the maximum packet length is 1/3 of the buffer capacity.

The calculation of the checksum in this implementation of the program is based on convolution modulo two, although any other algorithm can be applied. The received station packet verifies the correctness of the checksum and sends a receipt to the sender. Upon receipt of a confirmed receipt, the sending station destroys a copy of the sent packet in its buffer. Otherwise, this packet is transmitted rovtorno. The number of retransmissions can be limited and in case of a repetition counter expiration, it can be performed in accordance with the table. one.

For the connection of the node 12c, the device also uses a bidirectional SM data bus and the following control signals: Ready (YY) —to suspend the MP during the program's synchronization of transmitting information; ZPR1 - interrupt request 1 (inverse signal); ZPR2 - request for breaking 2 (inverse signal, the assignment of signals ZPR1 and ZPR2 are shown in Table 2); ZZH - request capture tires; RZH - permission to capture the tires.

The procedure of direct memory access is used in the process of receiving information into the buffer of the storage device and is described below.

When the supply voltage is applied to the device, the electromagnetic relay 14 is triggered and the communication line connects the diagnostic information provided by Q to the input of the receiver 1. When the subscriber is connected to the station.

The network functions include self-diagnosis procedures, which consist in the fact that diagnostic packages periodically circulate in the network, and the purpose of sending packages is to monitor the integrity of the ring line, to monitor the presence and status of stations operating in the network.

A permanent (reprogrammable) memory (ROM) 11 and a node 12 together constitute a control unit that functions in accordance with a control program algorithm.

The scientific research institute in the communication line of the start zero bit is set up by the trigger 5 and the signal from its output enables the operation of the counter 27 in the distributor 7.

The same signal arrives at node 12 as a request for an interruption of RR1, commanding the control program to start receiving a packet of information over the communication channel. Information from the output of receiver 1 also goes to switch 2

Depending on the state of trigger 9, switch 2 passes signals from receiver 1 output to transmitter 3 input (Transit mode) or

stored in the ROM 11, and the type of equipment from the output of the shift register 4 to the subscriber’s (user’s) input, the transmitter 3 (Transmit mode) connected to unit 13. In particular, 4K erasable ROMs can be used byte

The distributor 7 (Fig. 3) is started to generate clocking signals from all the nodes of the device, including

87604

(K573 series) and a microprocessor of the U880D or K1810BM86 type. As the block 13, the LSI of the serial receiving-transmitting device KR580BB51A is used, with which the output to the C2 and IRPS interface is realized. The operating memory of the control unit uses the information storage memory 25, for example, 4k-byte, and the storage device 6 uses its buffer 256 bytes. The address space of 64k bytes is used by the microprocessor in accordance with the specifics of its use in the device.

15e. Address buses with AO in A11 address the ROM 11 and memory 25, A12 is not used, A13-A15 are used to select memory 25 and generate commands

ve Address buses with AO in A11 address the ROM 11 and memory 25, A12 is not used, A13-A15 are used to select memory 25 and generate commands

management in accordance with the table. one.

For the communication of the node 12c with the device blocks, a bi-directional SM data bus and the following control signals are also used: Ready (YY) —to suspend the MP during the software synchronization process of transmitting information; ZPR1 - interrupt request 1 (inverse signal); ZPR2 - request for breaking 2 (inverse signal, the assignment of signals ZPR1 and ZPR2 are shown in Table 2); ZZH - request capture tires; RZH - permission to capture the tires.

The direct memory access procedure is used in the process of receiving information into the storage buffer and is described below.

When the supply voltage is applied to the device, the electromagnetic relay 14 is triggered and the communication line is connected to the input of receiver 1.

,

The SRI in the communication line of the start zero bit is set by trigger 5 and, the signal from its output enables the operation of the counter 27 in the distributor 7.

The same signal arrives at node 12 as a request to interrupt RR1, together with the control program to start receiving a packet of information over the communication channel. Information from the output of receiver 1 also goes to switch 2.

Depending on the state of trigger 9, switch 2 transmits signals from receiver 1 output to transmitter 3 input (Transit mode) or

from the output of the register 4 shift to the input of the transmitter 3 (Transmission mode),

The distributor 7 (Fig. 3) is designed to generate clocking signals from all nodes of the device, including

In addition to supplying the clock input of the microprocessor, the Quartz oscillator 26 has a direct and inverse output of the main frequency F and F (F goes to the microprocessor) and an output frequency F / 2. The receiver clock frequency divider on the counter 27 starts to work when it arrives at the input resetting the zero signal and the information storage device 6 (FIG. 2) is designed to receive serial information from successor 1, convert it into a parallel form, write to the buffer memory area 25

Fat the frequency F / 16 for synchronization-fO at sequential addresses and issue a register of 4. sign of the end of the information packet

Synchronization frequency divider (signal End of packet). As

The transmitter on the counter 28 is activated by a command. Transmission from the decoder 8, which switches the trigger 9 to the Transmit state and the signal Before, the output of the counter 28 becomes zero. From the output of the counter 28, the frequency arrives at the synchronization transfer register 4,

The elements are NOT 30, OR 31 and 32 n TjjHrrep 33 ff; are compiled to organize the programmed synchronization of the recording of information in register 4 for transmission from

The buffer zone uses 256 bytes of shared RAM 25. After a 5 positive-parallel converter, the register 16 is synchronized. It is synchronized with the Synchro signal received from the distributor 7 pulses from the counter 27.

20 of the next bit into register 16 occurs in the middle of the bit duration plus / minus T, which ensures reliable reception when the clock oscillators of the receiving and

20 of the next bit into register 16 occurs in the middle of the bit duration plus / minus T, which ensures reliable reception when the clock oscillators of the receiving and

The timing diagram of FIG. five.

Counter 15 after receiving the latter

using the Ready and Expanding Stations. Said record demanding (RZP). Circuit operation

illustrated by timeline

in fig 4. When setting the mode

Transfer, the program organizes its

work in such a way that after a bit has been shot, a byte produces a request for

allowance of information for writing to the direct access to the memory of the backup charger and increasing the buffer address at the counter 17 input. The enable signal of the direct access RZH returns to the initial state - 35, the counter 15, opens the bus drivers 21 and 22, generates a sampling signal memory 25, which is fed through input element 23 of memory sample 25, the same signal through 40 element HE 18 arrives at the input of trigger 19, which outputs the recording resolution signal, which through element OR 24 enters input recording permission ti 25. Temporary

with strobe entry TZH duration T 45 diagram of the procedure for writing bytes on

(period of the main frequency F). The direct access information is depicted in FIG. 6

gistr 4 command RZPD through 128 + 3 machine cycles to create the next byte of information. Then, the P31SH signal appears in the middle of the positive half-cycle of the transmission synchronization frequency on the last bit of the previous byte. From the output of the VGSH 31 to the end of the half period, a zero level of Readiness is issued, which puts the microprocessor in the idle state. At the end of the last bit output, the Ready level becomes 1, and on trigger 33, the output set by the microprocessor on the data bus is recorded in register 4 and from its output to the transmitter

When arriving from the channel byte

FF

sixteen

which is the sign of the written byte.

3, the first bit of the 50th packet begins to be output, and when writing this byte

In memory 25, a signal is generated. The end of the packet from the output of the element is AND 20. This signal resets the trigger 5. Thus, the request of the frequency divider structure for block 13 is removed, depending on the selected interface. For the variant: going to the junction C2 of the WGP1, which informs the IRPS microprocess, the divisor on the counter 29 should be about the end of packet reception and possible (five frequencies, kHz: 153.6-n

76.8-38.4-19.2-9.6 for work, corresponding information or transit package,

At the speed, at bit / s: appearing in the memory buffer 25.

9600-4800-2400-1200-600. In this case, asynchronous mode 1:16 should be programmed in USA1Sh (BIS KR580VB51A)

Information accumulator 6 (FIG. 2) is intended to receive serial information from successor 1, convert it into a parallel form, and write to the buffer zone of memory 25

by sequential addresses and issuing a sign of the end of the packet information

The buffer zone uses 256 bytes of shared RAM 25. After a 5 positive-parallel converter, the register 16 is synchronized. It is synchronized by a signal. The reception from the distributor 7 pulses from the counter 27 is synchronized.

20 of the next bit into register 16 occurs in the middle of the bit duration plus / minus T, which ensures reliable reception when the clock oscillators of the receiving and

25 transmitting stations. This is illustrated in the timing diagram of FIG. five.

Counter 15 after receiving the latter

When arriving from the channel byte

FF

sixteen

which is a sign of the packet, and when writing this byte

The starting address of the memory buffer 25 is taken to be L OO, which is reset to the initial state by the Start 1PC command from the decoder 8.

Claims (3)

1. A system for exchanging information containing M devices for transmitting and receiving information, each of which contains a receiver, a switch, a transmitter, a pulse distributor, a shift register, an information accumulator, a decoder, a reception trigger, and a transmission trigger, with outputs i-ro (i 1, M - 1) and M-th devices for transmitting and receiving information are connected respectively to the inputs of receivers (i + 1) -ro and the first device for transmitting and receiving information, and in each device transmitting and receiving information, the output of the receiver is connected to the first The control input, the output connected to the transmitter input, the control input of the switch are connected to the output of the transmission trigger, the first and second outputs of the pulse distributor are connected respectively to the clock inputs of the transmit and receive of the shift register, and that, in order to increase the system capacity, a control node, a permanent memory, an MI element, a block of communication registers with a subscriber, and a power supply voltage control relay, are introduced into each device for transmitting and receiving information. and in each transmission device and receiving information, the winding of the relay cont-40 Formation contains a memory, two bus The power supply voltage roll is connected to the poles of the power source of the information transmitting and receiving device, the power voltage control relay contacts are connected respectively to the receiver input and the transmitter output, the information input / output of the control unit is connected via a data bus to the information input of the shift register, information input output information accumulator, the output of the fixed memory and the information input and output of the block of communication registers with the subscriber, a group of inputs and outputs, and information control bits orogo are input-output device for connection information and control inputs and outputs correspond to the local system, and five address input - through the address bus connected to the address output of the control unit, address inputs of the information storage unit and the constant unit and the information input of the decoder, the control input / output of the control unit connected to the control and output of the storage unit information and a block of communication registers with the subscriber, the outputs of the receive trigger and the OR element, the third output of the pulse distributor and the control input of the decoder, the group of outputs of which is connected to the inputs of the sample of the fixed memory and storage information, installation and resetting inputs of the transmission trigger, the first input of the pulse distributor operation mode and the Start of direct access to the information accumulator, the information input of the serial code of which is connected to the receiver output and the receiving input of the trigger trigger, and the clock input 5 and output of the Packet end respectively, with the fourth output of the pulse distributor ,. the reset input of the receive trigger, the output of the OR element connected to the first input, the second input of which is connected to the output of the transmission trigger, the second and third inputs of the pulse distributor operating mode are connected respectively to the outputs of the transmission and reception trigger, the output of the shift register is connected to the second information input of the switch. 2. The system of claim 1, in which the drive in0 0 five shaper, two OR elements, shift register, AND element, bit counter, address counter, trigger and NOT element, the output of the shift register connecting it to the information inputs of the AND element and the first bus driver, the information input memory output is connected to the output of the first bus driver and information input-output 5Q by the storage of information, address memory input is connected to the address input of information storage and output of the second bus driver, information input connected to the output of the address counter, with ode input coupled to an output of the counter bit, and the installation input - to the input of Starting direct access storage media, input sampling and recording / read memory is connected respectively to the outputs of the first and second SHS elements, the first inputs of which are connected respectively to the input sampling information storage and output- 5 first inputs of the elements OR are connected the trigger house whose information input and sync input are connected respectively to the output of the NOT element and the clock input of the information accumulator, the information input of the sequential shift register code is the information input of the information accumulator, and the clock input is connected to the clock input of the information accumulator and the clock input of the bit counter, the installation input of which is connected to the second input of the first element OR, controlling the inputs of the first and second bus drivers and the element And, the input of the element NOT and the first control-20 reset input of the trigger and the counting input of the information accumulator, the house of the second counter, the installation output of the bit counter and the second input of the second element OR are connected to the control output and the second control input of the information accumulator. 25 the input of the pulse distributor connected to the second input and the output to the second output pulse distributor, the second input of the second element SHS and. through the element NOT to the second input of the first element OR, 3. The system of claim 1, distinguished from the fact that the distributor About About 1 1 About O 1 o one about pulses of the device for transmitting and receiving information contains a pulse generator, two counters, a trigger, two CMM elements and an NO element, and with the first input of the operation of the pulse distributor, and respectively with the third output of the pulse distributor and the counting input of the trigger, whose input is the first output of the pulse distributor, the output of the main frequency of the pulse generator is connected to the counting input of the first counter; the fourth output and the third input of the pulse distributor operating mode, respectively; the half-frequency output of the pulse generator is connected to trigger reset input and counting input of the second counter, the installation the input of the pulse distributor connected to the second input and the output to the second output pulse distributor, the second input of the second element SHS and. through the element NOT to the second input of the first element OR, Table 1 Selection of ROM Reserve Reserve Selection of RAM Transfer (before) Start SchCH (reception to the beginning of the buffer) Data Record for Transmission (DRR) Transit permit n . ZPR1 one 12987 0-12 table 2 Device state No reception (channel is free) Transit or Transmit mode is set. Information is being received from the channel, the transmission mode is set. Receiving information, set the mode Transit Prohibited condition FIG. 2  , Z6 % F / 2 Synchronization of the interde} ius / o o Before. pm Pu g J / J2 Log1 Jd - J3 Figz gshshshspshshtshggppppllllpll l J J JlJттуллJ J Issue 6 line of communication. Settlement / Noone Pita II  ± jr I 6 j Getting Started by , patch raoot, V X feed 6 j Getting Started by , pacala raoob GVyzhod on otklyu SVYHOG 1 jT HUfC power supply Guyod by disconnect one Fi.g.7 Widows from Podklnranmgo equipment M Indication of reception. Lee Will be in attendance Not FOR FORM-NR package wf Extradition t etao ring i CUD comparison aSpeca apatkatel in the package with the sbsbsg Vinnom address Expectation completion transit. Shut down transit Issuance to the ring Atliz dyA ML reception during 8redg transmission. I Transit recovery Waiting for the whale station Yes FULLED 5f / (pepa Preparing for the transfer L Editor E. Papp Compiled by V. Vertlib Tehred L. Serdyukova Proofreader S. Shekmar Order 891/52 Circulation 673 Subscription VNIISH State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Training Secondary transfer. (gfr / XO J Fig.Yu