SU1599864A1 - Device for exchanging data in computer network - Google Patents

Abstract

The invention relates to computing and can be used in local area networks as a device for exchanging data between local stations of the network and computing facilities of each local station. The aim of the invention is to expand the scope and improve the reliability of the network by providing the ability to initiate the exchange procedure and control data transmission. The goal is achieved by the fact that the device containing the processor 1, the system controller 2, the priority interrupt unit, the blocks of permanent and main memory, the 6 clock pulse generator, the communication synchronization block 7, the control decoder, the state analysis block, the block 22 control of the waiting time of the response, block 23 of control of the communication time, block of control of the waiting time of the exchange, block of bus drivers and element I. 6 Il.

Description

SP

wasp

O5 4ib

containing a processor 1, a system controller 2, a priority interrupt unit, permanent and main memory units, a clock generator 6, a communication synchronization unit 7, a control decoder, a state analysis unit, a response time control unit 22, a unit 23 control of communication time, block of waiting for exchange time, block of bus drivers and element I. 6 Il.

The invention relates to computing and can be used in local area networks as a device for exchanging data between local stations of the network and computing facilities of each local station.

The aim of the invention is to expand the field of application of the device and improve the reliability of the network by providing control of data transmission and the possibility of initiating the exchange procedure.

Figures 1 and 2 show the structure of the device for the exchange in the computer network; FIG. 3 shows an example of the implementation of a control unit for waiting time for a response; 4 is the same, the communication time monitoring unit; FIG. 5, the same, the communication waiting time control unit; in Fig.6 - the same, the block of the PN shaper.

A device for exchanging data in a computer network (Figures 1-2) contains a processor 1, a system controller 2, a priority interrupt unit 3, blocks of a constant 4 and a random 5 memory, a generator of 6 clocks, a block of synchronous communications, a decoder 8 controls, a channel condition analysis block 9, a group of T address outputs, including the first 10.1 and second 10.2 bits, the twelfth 10.3, the thirteenth 10.4 and the fourteenth 10.5, and the fifteenth 10.6 bits, the control outputs 11. reading, 11.2 writing, and 12 CPU synchronization, bus 13 data devices, information link 14, first to fifth 15.1, 15.2, 16-18 generator outputs 6 clock pulses, initial installation bus 19, external interface highway 20, first bit 21.1, second bit 21.2 of group 21 of the outputs of state analysis unit 9 channel, control unit 22 waiting time response, unit 23 control communication time, block 24 contact

five

0

50

Q d o

five

a role of waiting time for an exchange, block 25 of bus drivers, element I 26, first-third 27, 28.1, 28.2 outputs of block 22 controlling wait time for response, address bus 29, first 30.1 and second 30.2 outputs of block 23 controlling communication time, output 31 of block 24 control of waiting time of exchange, group of outputs of address 32, control 33 and data input-outputs 34 of bus driver unit 25, output 35 of acknowledgment of processor 1, readout outputs 36.1 and write 36.2 of system controller 2, output 37 of acknowledgment of reception of interrupt request of system controller 2, group 38 block data input-output 3, the output 39 of a request for interruption. unit 3, generator installation output 40, output 41 of communication synchronization unit 7, first 42, second 43.1, third 43.2, fourth 44 and fifth 45 outputs of the decoder 8, group 46 of the control outputs of the device, control output 47 of the block 9 , input – output 48 of the device data, input 49 of the device’s response blocking, first 50.1, second 50.2, third 50.3 bits of the device input 50 group, high bits 51, response bus 52 of the external interface trunk 20.

The response time control unit 22 (FIG. 3) comprises a trigger 53, a first 54, a second 55 AND elements, AND-NE 56, 57, a diode 58 and a capacitor 59.

The communication time control unit 23 (FIG. 4) contains the first 60 and second 61 triggers, timer 62, element HE 63, transistor 64, capacitor 65, resistors 66 and 67.)

Block .24 of monitoring the waiting time of the exchange (Fig. 5) contains a timer 68, a HE element 69, a transistor 70, a capacitor 71, resistors 72 and 73.

Block 25 Tirenn Shaper (6) contains the first 74 and second

75 blocks of trunk elements, the first 76 and second 77 trunk elements.

The processor 1 is designed to control the exchange of data and control information in the device in accordance with a predetermined network protocol and process the interrupt signals from the control units.

System controller 2 is designed to store information about the work performed by processor 1 during a computer cycle, as well as to control individual elements of the system of the device.

Unit 3 is designed to ensure the organization of the exchange of information in the interrupt mode from the control units of the device and in the process of receiving information. Block 3 allows a simple priority interrupt mode (when implemented, all interrupt request inputs are assigned fixed priorities.

Permanent storage device 4 is intended for storing programs that determine the operation of the device when exchanging data in a computational network.

Random access memory 5 is designed to store the current transmitted and received information, RAM 5 implies several zones. The distribution of information by zones can be following:

the area of the computer network configuration, which includes the list of own addresses of devices for data exchange, similar to those claimed, which are connected to the local network;

the byte zone of the channel status, transmission, reception, termination;

working cell area;

transmission buffer area to communication channel

buffer zone. reception from the communication channel

zone of the additional buffer of reception from the channel: communication,. The clock generator 6 is designed to generate two time-non-intersecting sequences of pulses of pulses necessary for the operation of processor 1, synchronization of the output to processor 1 of the reset and readiness signals, as well as

ten

20

five

state gate and sync signals.

Unit 7 is designed to generate a ready signal based on input control signals from the elements of the device.

The decoder 8 is designed to generate signals controlling the elements of the device.

Block 9 is designed to control the operation of the elements of the device for data exchange and the transceiver associated with it, taking into account the state of the J5 channel (the presence or absence of information in it),

The unit 22 is designed to provide monitoring of the transceiver's health by waiting for a response from it by the processor 1, as well as to generate control signals for the transceiver, communication synchronization unit 7 and priority preemptive unit 3.

Block 23 is designed to monitor the transmitter failure by continuous data generation to the communication line (exceeding the allowable communication time),

Unit 25 is designed to control the exchange and exchange of address, control signals and data, respectively, taking into account control input signals.

The device works as follows.

The exchange of information in the network between local stations is organized in the form of cycles, by which is meant the procedure of transmitting to the communication channel one communication package (message). Several interconnected cycles form the transmission process, which in general is organized according to the asynchronous principle. This means that the device should receive answers to calls sent to the communication channel, the data exchange between local stations in the network is realized, for example, the IRM 0 interface (GOST 26139-84, Interface for automated control systems for distributed objects), in this case information transfer between local stations is accomplished through a limited set of bytes, the order of which is determined by the message format. A device may perform several network functions, the code of which is specified in the message format by the byte containing.

0

S

S

five

information about the type of message, the sign of the local station's occupation, the type of message format, the sign of the 1 second transmission.

The local station can perform the following functions, which determine its place at the appropriate level of control transfer in the network: reception - answer, centralized control.

When performing the appropriate. local station functions are considered active relative to this function. Depending on the functions performed by the device at a given time, the following three types of state of local stations are distinguished: a controlled subsystem; management subsystem; leading subsystem

Transitions between the states of local stations are carried out in accordance with the accepted network data exchange algorithm. In the Managed subsystem state, messages addressed to the device are received and response messages are generated in accordance with the code of the network function implemented. In the Initiative control state, the device subsystem can receive the exchange control over the communication channel, form and transmit, report, receive and analyze response messages, and also return control after the transfer process is completed. In the master subsystem, the device implements the coordination of the operation of all devices connected to the communication channel. In this case, the master device can transfer control to another device and control the operation of the initiative controlling device. Coordination of local network stations is carried out by the network master by performing the transfer and return functions of control. When transmitting the control, the master device assigns one of the numbers present in the network to the active control device for transmitting the message. In this state, the master device sends a Transfer Control Channel message to the selected local station. After receiving the message, the selected station may perform one exchange cycle in one transmission procedure. By

0

five

0

five

0

five

0

five

0

five

At the end of the transmission process, the initiating control station completes the return control function, for which it sends a Return Channel Control message to the master. The transfer of control can be ocy-j only initiated by the master system. The data transfer procedure is carried out when performing the network recording function. In this case, the master device or the initiative control unit forms a message on the communication channel with the Record function, which is addressed to a specific local station. The addressed device recognizes its own address in the message and issues a message acknowledgment message to the communication channel. After a message is issued, the issuing device makes a software readout of the control time interval, awaiting a response message. In the absence of a response after the control interval expires, the transmitting station performs a three-time retransmission of the same message. If there is no response after a three-time reloading, the address of the device in question is considered reject. During an exchange with an addressable device, the master station performs the function of passively receiving messages.

The main modes of operation of the device are the initial launch and the reception and transmission (exchange) of data.

When the system starts up, the system enters the initial start-up mode from the interface bus 20 via bus 19 to a setup signal to the clock pulse generator, from output 16 of which the signal goes to the input of the microprocessor 1's initial setup. At the same time, its program command counter is cleared; neither interruption nor seizure - so gaine. After that, processor 1 proceeds to the implementation of the initial startup program. The signal from the output 40 of the oscillator 6 clocks element And 55 forms a low level signal Reset the transceiver, which from output 27 goes to the same line bus 46 to bring the transceiver back to its original state. During the initial startup program

In RAM 5, clearing the list of local station addresses, status bytes, resetting ready bytes, setting up priority interrupt block 3, after which the device is considered ready to exchange information.

Further, the device implements the procedures for the exchange of information with input-output modules connected to it via trunk 20, with other local stations via a communication channel. At the same time, the operation of the own information transmission means and other stations in the network (in particular, the master) Only one device in the local computer network can be the master and control the channel. All other devices included in the network are passive and activate. after transferring control to it. Any device entering the network analyzes the information circulating in the communication channel in order to detect the message addressed to it. The fulfillment of this function is realized by the following yuschim manner.

If there is information in the communication channel, one of the lines of the group 51 of the inputs of the analysis block 9 is excited, which leads to the formation of an interrupt signal on line 21.1, which is fed to the input of block 3, which causes its output 39 to generate an interrupt signal, which is fed to the processor input L of the same name, Processor 1 on bus 14 generates a status word code, and output 11.1 produces a Read signal. This causes the output 37 of the system controller 2 to generate an interrupt acknowledgment signal arriving at the same input of block 3. In addition, the signal from the output 37 of the Teivflioro controller 2 is fed to the input of block 22. Block 3 sends a command to bus 13 to the device data bus 13 call the service program of the interrupt. The interrupt confirmation signal from the output 37 of the system controller 2 in block 22 generates a signal, which from output 28.2 enters the input of block 7 and at its output generates a ready signal arriving at the input of generator 6. At the output 17 of the generator, one forms

ten

15

20

 ), - 25

: 59986A About

The name of the signal attributed to the ready input of the processor 1. After this, the processor 1 decouples the call command and proceeds to the execution of the service program. When the transceiver is addressed to the address set on bus 10 by processor 1, control finisher 8, at output 43.1, generates a call signal to the internal elements of the system, after which the channel status analyzer 9 reads the read signal of the transceiver state register. The signal from the output 43.1 of the control panel 8, in addition, is supplied to the communication unit 22. At the output of element 5, a high potential is formed (since in the exchange mode the signal at input 49 is high). In case of waiting for a response from the transceiver to the signal of the processor 1 to it, the capacitor 59 is charged and at the output of the element 56 a low level signal is set, which sets the trigger 53 into a single state, which causes a high-level interrupt signal to be generated at its single output from output 28.1 of block 22 goes to block 3. Thereafter, the device proceeds to service the interruption of the interrupt request. By the interrupt acknowledge signal from the output 37 of the system controller 2, the trigger 53 is set to the zero state. The signal to access the internal elements of the device, coming from the GPR line 43 of the inputs of the synchronization unit 7, together with the transceiver readiness signal, arriving via line 50.2, causes Shrovapie forcing the output 41 of the synchronization signal of the communication signal of the transceiver to be exchanged, 6 clock pulse generator input. This, in turn, causes the generator to generate 17 pulses at the output, post-processor input to processor 1. After that, processor 1 reads the status of the transceiver and the data from it.

After selecting the addressed message, the device monitors the correctness of the message reception and function code. If the information is received incorrectly, the system proceeds to execution.

thirty

35

40

45

50

55

channel state analysis algorithm. If the information is received correctly and a message with the Record function code is received, the device will receive (analysis of reception buffer reception from the communication channel. If the buffer is empty, the device sends a response message with the Confirmation code to the channel) transfer information from the claimed device to the communication channel is carried out similarly to reception. Only the direction of the transfer is changed by the formation of corresponding address bits on bus 10 and the signal Is output 11.2 coming to the system controller 2, which generates control signals by the channel state analysis unit 9. When receiving information from the channel and transmitting it by the unit 22, the transceiver is continuously monitored for a predetermined response time from it. the communication channel is busy, the device transmits to the communication channel a response message with a buffer occupancy sign and proceeds to the implementation of the communication channel state analysis algorithm. Since each device entering the network is assigned its own code for the waiting time for the transition to the master mode, when there is no information in the communication channel after the waiting time interval monitored by the program has elapsed, the program proceeds to implement the master program. . During the execution of the master program, control transfer is organized for each local station included in the network configuration list stored in the corresponding zone of RAM 5, and information from the communication channel is monitored. If there is no information in the communication channel, i.e., none of the local stations of the network responds to the transfer of control, the master device relieves itself of the functions of the master and proceeds to the implementation of the program for analyzing the state of the communication channel in the same way as described above. In this case, the program for analyzing the state of the communication channel is executed until the channel does not receive information or does not expire

0

five

shaft waiting time to transition to the leading function. If the information with the control transfer function code is present in the communication channel, then the device generates a control return function code in response and proceeds to the execution of the program of the initiative controlling or controlled system.

The communication of the device with I / O modules connected to it via trunk 20 is implemented as follows.

The processor 1 on the bus 10 forms

, address addressing the corresponding I / O module. This is transmitted; high potentials, respectively, at the inputs 10.2-10.5, which causes the output of the 43.2 control decoder 8 to generate a low-level signal for accessing the external elements, which controls the blocks of 25 linear drivers and 7 communication synchronization. Depending on the operation performed by the processor 1 to receive or transmit information to the I / O modules, control signals are generated at its corresponding outputs (11.1 or 11.2), on the basis of which information transmission direction is determined by the system controller 2 and the like signals are output at outputs 36.1 or 36.2 control signals, arriving at the inputs of the bus driver unit, will initiate: herewith, the transmission or reception of information to / from the input-output modules. After identifying the access signal, the I / O device that recognized it generates a Response signal, which via line 52 of the interface bus 20 is fed to the input of communication synchronization unit 7. In this case, a readiness signal is generated at its output, which is fed to the corresponding input of the generator 6 and initiates the formation at its output 17 of a readiness signal, which is fed to the same input of processor 1,

Alert him about the ability to read (data) data from / to the bus 13 data. When transmitting data to a communication channel, the device monitors the operability of the transmitter by tracking the duration of the transmission quantum. Information about the start of the transmitter operation enters the system via line 50.3 of the group of inputs 50 of the transceiver. If the working time is transmit

five

0

five

five

one-

If the sensor exceeds the permissible time of the information transfer cycle, then the capacitor 65 will have time to charge up to a high level of the signal, exceeding the trigger level of the timer 62 in the threshold input. A low level pulse is generated at the timer output, the duration of which is determined by the discharge time of the capacitor 65. The generated low level signal from the output 30.2 of the communication time control unit 23 arrives at the input of block 22 and causes the transceiver to generate a signal. In addition, the pulse from the output of timer 62 is inverted by the HE element 63 and is fed to the sync input of the trigger 61, sets it to the zero state and thereby forms at the output 30.1 of the block 23 the processor 1 interrupt signal when the transmitter exceeds the allowed transmission time to the communication channel . The operation of the system for handling interruptions occurs in the same way as described above. After sensing the interrupt signal, processor 1 proceeds to the execution of the service program of this type of interrupt.

If the transmitter operation time has not exceeded the allowable, then no signals are generated by block 23 and the device operates in accordance with the programs stored in ROM unit 4 and the information recorded in the corresponding zones of RAM 5.

In addition to the described type of control, the device implements control of the waiting time of the next exchange cycle over the communication channel. Upon completion of the transmitter on line 56.3, a low level signal is established, inverted by the NOT element 69 of block 24. The high level signal from the output of the NOT 69 element is fed to the start input of timer 68 and the base of transistor 70. Capacitor 71 starts charging. The time of its charging is calculated for the time of the beginning of the next cycle of information exchange over the communication channel of the claimed system with other stations. If the next exchange cycle is initiated out of time, for example, there is a deadlock in the organization of interaction between the local stations of the network, then the capacitor 71 will have time to charge to the threshold level and at the output of the timer 68 will be formed low level 9864

ten

15

a new interrupt signal coming from the output 31 of the block 24 of the monitoring of the waiting time of the exchange to the input of the block 3 of the priority interruption. This interrupt request is serviced in the same way as described above. In the case when the next exchange cycle starts in a timely manner, the signal level on the line 50.3 changes with switching on the transmitter and block 24 does not generate an interrupt signal.

Claims (1)

Invention Formula 25 20 thirty A device for exchanging data in a computer network, comprising a processor, a system controller, a priority interrupt unit, a fixed and random-access memory block, a clock generator, a synchronous communication unit, a control decoder, a channel state analysis unit, and an address output group processor is connected to the same input of a group of blocks of constant and main memory, the output of the first bit of the group of address outputs of the processor is connected to the same input of a priority interrupt unit, The first and second bits of the group of address outputs of the processor are connected to the same inputs of the channel state analysis block, the outputs of the twelfth and thirteenth bits of the group of address outputs of the processor are connected to the first and second inputs of the decoder, and the outputs for controlling the read, write and synchronization of the processor are respectively connected with inputs for reading, writing system controller and with synchronization input of clock pulse generator 5, the first input-output data of the signal controller through the same name bus u is connected to the input-output data of the blocks of permanent memory, RAM, priority interrupt and input-output data of the device, the second input-output data of the system controller is connected to the input-output data of the processor, the outputs from the first to fifth generator are connected respectively with the first and second synchronization inputs, the reset and readiness inputs of the processor and the synchronization input of the system controller, the output of the second digit of the interrupt code 35 40 50 55 the group of outputs of the state analysis block is connected to the third time input of the interrupt request interrupt block of the priority interrupt; the input of the initial setup of the clock generator is connected to the bus of the same name. external interface trunk and is the input of the device, characterized in that, in order to expand the scope and improve the reliability of the network by providing the ability to initialize the exchange procedure and control data transmission, it introduces blocks of control of waiting time for response, control of communication time, control waiting time of the exchange, bus drivers and the element And, and the outputs from the first to the third block control the waiting time response is connected respectively to the output device reset, The first and second outputs of the communication time control block are connected to the fourth bit input of the interrupt request, respectively, with the input of the first bit of the request for interrupting the preemption block and the first information input of the synchronization unit of the communication. The priority interrupt unit and the first information input of the response time control unit, the output of the exchange time control unit, is connected to the fifth search input of the priority interrupt request unit, the address outputs, data input-outputs and the control outputs of the bus driver unit B-. are input inputs of the device, the output of the confirmation of waiting for the processor is connected to the second information input of the control unit of the response time, the output of the system output the controller is connected to the first input of the bus driver unit, the read input of the permanent memory unit, the read input of the state analysis unit and the read input of the priority interrupt, the write output of the system controller is connected to the second by the mode input of the bus driver unit and the write inputs of the operative block memory, analysis of the channel status and priority interruption, the output of the confirmation of the interrupt of the dark controller is connected to the third information input of the control unit of the waiting time for the response and dyh; 0 five 0 five 0 five 0 45 50 55 The interrupt acknowledgment house of the priority interrupt unit, the interrupt request output of which is connected to the processor input of the same name, the output of the clock generator setting is connected to the fourth information input of the response time control block, the first output of the decoder is connected to the control input of the priority priority block, the second output of the decoder connected to the fifth information input of the control unit waiting time response, controlling the input of the state analysis block and the second information input ohm synchronization unit, the third output of the decoder is connected to the input selection of the bus driver unit and the third information input of the synchronization unit, the fourth and fifth outputs of the decoder are connected respectively to the input of the constant memory selector and the synchronization input of the operating memory, the output of the first bit of the information output group The state analysis block is connected to the second bit input of the interrupt request block of the priority interrupt, the output of the block address of the analysis block is the device of the same name, The output of the state analysis unit is connected to the first input of the communication time control unit, the inputs of the first, second, third bits and most significant bits of the control information of the device input group are connected respectively to the second information input of the communication time control unit, the fourth information input of the unit synchronization, information input of the control unit for waiting for the exchange and the control input of the channel state analysis unit, the third information input of the control unit for communication time is connected to the information the input of the control unit for the waiting time of the exchange, the blocking input of the response of the device is connected to the sixth information input of the control unit for the response time and the fifth information input of the synchronization unit of the communication; the input of the response of the device is connected to the sixth information input of the synchronization unit whose output is connected to the input readiness of the generator of clock pulses, the outputs of the fourteenth and fifteenth bits of the address of the group of address outputs of the processor are connected respectively to the first and second inputs of the element And, the output of which is connected to the third and fourth inputs of the decoder, the group of address outputs by microprocess (. 2 Pa connected to the information inputs of the group of block bus drivers, a group of inputs-outputs of which are connected to the input-output data of the device. Fi9. FIG. four Ru sh about v4j ° R R15 J / o 1 zH