SU1545311A1 - Dc voltage-to-three-phase quasisine voltage converter - Google Patents

Abstract

The invention relates to electrical engineering and can be used in secondary power supply and electric drive systems. The purpose of the invention is to increase reliability by reducing the voltage on the alternating current keys and reducing the weight and size. The converter contains the main and auxiliary single-phase inverters, made on the keys 1 - 4 and 5 - 8, respectively, and loaded on the primary windings of the main 9 and auxiliary 10 transformers. The first, second and third secondary windings 11, 12 and 13 of the main transformer and secondary windings 14, 15 of the auxiliary transformer are interconnected and connected to the output terminals A, B, C of the converter via AC switches 16 - 27. With a certain switching algorithm of alternating current switches 16–27 and switches 1–8 of the main and auxiliary single-phase inverters, the phase output voltage of the converter has an 11-step form, which is close to sinusoidal. 1 hp f-ly, 4 ill.

Description

The exclusion refers to electrical and can be used with a secondary power supply and; IVIIU.MUI.

 nsobrannln - ponyasnie on H (.1, GT1, nyicM / mony eni voltage and lh-1h ucp.-VL HHoro current and ump-: V g, h mage and 7) 0aritov.

1-1 fnl. 1 shows the prnntsinn-) |, .ts cvpMa sigovy part ireog r, chcho- and.-. t-g - n; in fig. 2 - principle .x- ii control systems transform-ii-t; in fig. 3 - diagrams, in sun. - the principle of the formation of pulses up1), by the keys of the transformer 4, on i Mi1. 4 - Gaols of truth of progr-chm with the power of a persistent memorable will arrange a run.

 popbrach.gsgs-lb (Fig. 1) contains and. n vnioii and auxiliary single-phase Hiii inverters, made accordingly (chnm on keys 1-4 and 5-8. The outputs of the inverters are loaded on the primary windings of the main and auxiliary transformer 9, JO. The first, second and third secondary windings of JJ-13 the main transformer 9 and the secondary windings 14, 15 of the auxiliary transformer 10 are connected between each other and through the keys 16-27 of the alternating current with the output terminals A, B, C of the converter,

The converter control panel (Fig. 2) contains a master oscillator 28, the output of which is connected via a trigger 29 and a block 30 of buffer cells with control inputs of keys 1–4 of the main inverter. In addition, the output of the sub-switch master oscillator 28 is through a frequency divider 31 with a variable division factor to the input of a binary counter 32, the outputs of which are connected to the address inputs of the programmable constant electronic device 33. The outputs 34-49 of the latter are connected via trigger 50 , logic elements 2-2И-2Ш1И 51-63, elements NOT 64-66, elements 2И 67 and 68, block 30 with control inputs of the power switches of the converter, and the output numbers of block 30 correspond to the numbers of the keys to which they are connected. ,

FIG. 3, diagrams 69-91 represent the pulse shapes at the outputs of the following elements: 69 — master oscillator 28, 70, 71 — direct and inverse outputs of the trigger 29 (key control pulses 1, 4 and 2, 3 inverters); 72 - CG divider; 73 - 76 - elements 51, 64, 52, 65 (impulses of control keys 5-8); 77, 78 - transformers 9, 10; 79 - 90 - elements 67, 68, n 54 - 63 (key control pulses 16-27); 9 1 - conversion (GA output phase direction).

The device works in the same way.

The output voltage curve in the converter is improved by pulse-amplitude modulation, and the weight and size of the transformers is reduced by converting the DC voltage to AC at a high intermediate frequency.

The master oscillator 28 (Fig. 2) generates a sequence of pulses 69 (Fig. 3), which is fed to the input of the trigger 29. The signals 70, 71 of its direct and inverse outputs are amplified by the block 30 of the buffer amplifiers and fed to the control inputs of the power switches 1, 4 and 2, 3 main inverter. In addition, the frequency of the master oscillator 28 is divided by a frequency divider 31, for example two, and fed to the input of a binary counter 32 with a scaling factor of 21. From the counter outputs 32, the pulses go to the address inputs of the programmable memory 33, the logic states of the outputs 34 49 which, depending on the address code, is presented in the table in FIG. 4. The output signals of element 33 allow or prohibit the passage of pulses 70, 71 from the direct and inverse outputs of trigger 29 to the inputs of block 30. Moreover, the logic zero level at the input of block 30 provides the closed state of the power switch of the converter, and the logic one level is open . The trigger 50 and the logic elements 53 and 66 invert the pulses of the direct and inverse outputs of the trigger 29, the input elements 67, 68 and 54, 63 through the half-period of the output voltage of the converter. In the first half period, the signal of the logical unit of the output 38 of the element 33 is set to the logic state 1, and a direct sequence of pulses from the output

515

ipmrep i 29. In the second half-period, the trigger BO switches to the state O, and the inverse signals from the output of the trigger 29 pass to the output of element 53. Such a change of pulse sequences is determined by the operation algorithm of keys 16-27 (diagrams 79-90, Fig. 3 ). The half-period of the output voltage 91 of the converter can be divided into 21 equal intervals, which corresponds to the 21st state of the element 33

In the first interval, in accordance with the table of FIG. 4, the logic unit signals from the outputs 34, 37, 41, 42, 44 of the element 33 ensure the passage of a direct sequence of pulses from the output of the trigger 29 through the elements 51, 55, 56, 58 to the control inputs of the keys 5, 19, 20, 22 and by inverting the pulse train through elements 52, 54, 57, 59 and block 30 of the buffer amplifiers to the control inputs of keys 7, J8, 21, 23. In addition, the output pulses of elements 51, 52 are inverted by elements 64, 65 and through block 30 arrive at the control inputs of the keys 6, 8 auxiliary inverter. The signals of logical zeros from the outputs 39, 46 - 49 of the element 33 lock the elements 67, 68, 60-63, and hence the power switches 16, 17, 24-27. The control pulses are generated at all intervals of the power switches of the converter at the following intervals as described in accordance with diagrams 69-90 (Fig. 3) and the truth table (Fig. 4) of element 33. As a result of the operation of inverters, rectangular wires are formed on the windings of transformers 9, 10 77, 78, and in the load phase, when connecting its star voltage, the voltage is 91, / close in. form to sinusoidal. The amplitudes of steps 1 through 11 of this voltage

U „5U 7U 8U,„ 10U 1Ш are equal -, U, -, г-, 2 - з

4TJ, -г-, -г-, where U - amplitude nap

The windings 13, 14 of the auxiliary transformer 10 must be equalized. To obtain voltage with the indicated amplitudes, the voltage levels on the secondary windings 11-13 of the main transformer 9 must be equal to 2U, 3U, 2C, i.e. The number of turns of the windings 11-13 of the main transformer 9 and the windings 14 and 15 of the auxiliary transformer 10 should be referred to as 2: 3: 2:: 1: 1.

The main and auxiliary inverters and transformers can operate at any high frequency that is a multiple of the output frequency of the converter. In this case, the frequency multiplicity is determined by the division factor of the frequency divider 31 and the number of steps in the half-period of the output voltage. Let the division factor of the frequency divider 31 be, for example, two. The interval of each voltage level 91 can be divided into two subintervals, corresponding to the half-life of the transformer 9.

On the first subinterval of the first interval, close the keys 1, 4, 5.8,

19.20, 22 (diagrams 70, 73, 76, 82, 83, 85 FIG. 3). In this case, the voltages on the secondary windings Jl: -13 of the main transformer 9 are respectively 2U, 3U, 2U, and on the secondary circuits 14-15 of the auxiliary transformer 10 are equal to TJ. The output pins A, B of the converter, through closed keys 22 and 19, are applied an algebraic sum of the voltages 12-14, equal to 4U, to the terminals B, C through the keys 19, 20, the sum of the voltages 11, 12, 13, is (-7U ), to conclusions C, A - through keys

20.22 - the sum of the voltage of the windings 11 and 14 is equal to 3U. In this case, when the star load is connected, the phase voltages are

U

-

 4U - 3U U

j s;

U6C - U

s

-7U - 4U -JJ

and,

Uc - (ue-ue) .lf2.

In the second subinterval of the first interval, the keys 2, 3, 6, 7, 18, 21, 23 close the polarity of the voltages on the windings of transformers 9 and 10. Algebraic sum of the voltages of the windings 11, 12, is applied to the output pins A, B, 15 equals 4U, to conclusions B, C - the sum of the voltages of the windings 11 - 13, is equal to (-7U), to conclusions C, A - the sum of the voltages of the windings 13 and 15 is equal to 3U, therefore the values of linear and phase voltages remain the same . Subsequently, in the first interval, at any division factor of the frequency divider 31, the operation of the alternating current keys is repeated for odd and even subintervals, respectively, and the first positive, eighth negative, seventh positive phase voltages UA, Ub, Uc are formed, respectively.

In the first subinterval of the second interval, the keys 1, 4, 5, 7, 19, 20, 22 close the polarity of the voltages on the windings 11-13 of the main transformer 9, and the voltage on the windings 14, 15 of the auxiliary transformer 10 becomes zero. The sum of the voltages of the windings 12, 13 is equal to 5U to the terminals A, B, the sum of the voltages of the windings 11, 12, 13 is equal to (-7U) to the terminals B, C, the voltage of the windings 11 to the terminals C, A equal to 2U. In this case, the phase voltages of the windings become equal Id And Uv -4U, Bs 3U, i.e. a second positive is formed, the ninth is negative, and the pole is a positive phase voltage step.

In the future, the converter is operated in the same way as described in accordance with diagrams 69-91 (Fig. 3 of the control pulses of the converter keys.

Connecting any branch of the circuit using alternating current switches provides the possibility of current flow in two directions and the constant potential difference of the phases during each interval. This determines the efficiency of the converter at any load power factor with a constant output voltage curve.

In the proposed converter, the voltage applied to the AC switches is reduced and reduced.

the mass of the main and auxiliary transformers.

Claims (2)

1. DC / DC converter to three-phase quasi-sine-wave voltage, containing primary and auxiliary single-phase inverters, outputs connected to the primary windings of the main and auxiliary transformers, the first of which contains three secondary windings, and the second - two secondary windings, as well as four groups of alternating current keys, three keys in each group, one power outputs of which are connected to the corresponding output terminals of the converter, and other power outputs of the keys of each group Four common points are combined and form, of which the first and the fourth are connected to the beginning of the first and the end of the third secondary windings of the main transformer, so as to increase reliability by reducing the voltage on the AC switches and reducing the weight and size , the combined beginning of the second and the end of the first, as well as the beginning of the third and the end of the second secondary windings of the main transformer are connected separately through the secondary winding of the auxiliary transformer with common points of the second and third Nos AC keys respectively. 2. A converter according to Claim 2, characterized in that the number of turns of the first, second and third secondary windings of the main transformer and the secondary windings of the auxiliary transformer relate to each other as 2: 3: 2: 1: 1. I INSIfSJ J o  C liva  G and "" a fQ "  fe milllllllllllllllllllllllimmmimilllllllllllllllllllllllllllllllllllinHll t 69 70 77 U 73 74 75 tf ppppppppppppppppppppppppppppppppppppppppp t chpppppppppppppppppppppppppp nnnnnnnrmnnnnhmt ppppppppppppppppppppppppppppppppppppppppppppppppp I, I, I, I, I, I, I, I, I, I, I I I I I I I I pp p pppp p pppp p ppppp p pppp p pppp p pp nn n pppp p rppp ppppp p ppppp ppptn n nn f ppppppppppppppppppppppppppppppppppppppppp p t ppppppppppppppppp ppppppppppppppppp ppppppppppppp b / 81 LZNppp ppppppppp tppppppnn n a ppppppppp ppppppppppppppppp pppp ppppppppppppppppp L51PP ppp 87 nnnnn ppp ppp ppp ppp 90 pprp ppppppppppppppppp ppppppppppppppppp ppppppppppppppppp tpp ppppppppppppppppp tpp hipp ppppplpppp t Ppp1ppp nnn t ppppp tpp t ppp ppp sapp sapp SPP GSR. fi & w