SU1112510A2 - D.c. voltage-to-three phase a.c. voltage converter - Google Patents

Abstract

CONVERTER VOLTAGE CONVERTER TO THREE-PHASE VARIABLE on auth.St. No. 970607, characterized in that, in order to reduce the weight and dimensions, a variable AC key and two secondary windings of an additional transformer are inserted into it, each extreme terminal of the main transformer is additionally connected via an AC key to the output terminals of the opposite arm converter, and the intermediate terminal of each half winding is connected via the secondary winding of the auxiliary transformer and the AC switch to the output terminal. the transducer of this arm. W

Description

1 The invention relates to converter technology and can be used in power supply and electric drive systems for converting a constant voltage to a three-phase AC. According to the main auth. No. 970607 is known a three-phase alternating voltage constant-voltage converter, containing a main single-phase inverter with an output transformer, the middle point of which is formed by one output voltage of the converter, and the extreme terminals of the transformer are connected to the first and second ac keys of the transformer. the other two of its output pins, the third fourth controlled keys of alternating current, an additional single-phase inverter with two output windings of the output transformer, which are one of The outputs are connected to taps from the middle points of the secondary windings of the transformer primary transformer, and other outputs through the third and fourth controlled alternating current switches to the corresponding output terminal of the opposite arm, while the number of turns of one section of the secondary winding of the main transformer and secondary winding of the additional transformer choose from the ratio of 2: 1. The main and auxiliary inverters and transformers operate at different frequencies and must be designed for frequencies 3 and 5 times higher than the output frequency of the converter. The voltages of the secondary transformers are algebraically summed and a three-phase four-stage voltage is formed. A disadvantage of the known converter is the large mass and size, especially at a low output frequency of the converter. The aim of the invention is to reduce the weight and size of the converter. The goal is achieved by introducing four AC switches and two secondary windings of an additional transformer into a three-phase AC converter, each extreme terminal of the secondary winding of the main transformer is additionally connected via an AC switch 102 to the output terminals of the opposite arm, and the intermediate terminal of each half winding is connected via the secondary winding of an additional transformer and an AC switch to the output terminal the transducer of this arm. FIG. 1 shows an electrical schematic diagram of the proposed converter in FIG. 2 - block circuit of the converter control unit; in fig. 3 shows diagrams explaining the operation of the device; FIG. 4 is a memory state truth table. The converter (Fig. 1) contains the main 1 and auxiliary 2 single-phase inverters, made respectively on switches 3-6 and 7-10. The outputs of the inverters are loaded on the primary windings of the main 11 and auxiliary 12 transformers. The secondary winding of the main transformer II contains the middle terminal 13, which is directly connected to the second output terminal of the converter (phase B). The first half winding contains the first extreme 14 and intermediate 15 terminals, and the second semi-winding intermediate terminal 16 and the second extreme 17, which, together with the middle terminal 13, divide the secondary winding of the main transformer into four equal sections 18-21. To the intermediate terminals 15 and 16 are connected with one ends of the secondary windings 22-25 of the auxiliary transformer 12, the second ends of which, together with the ends 14 and 17 of the secondary winding of the main transformer 11, are connected via alternating current keys 26-29 to the first output terminal of the converter (phase A) and through the keys 30-33 s / third output output (phase C). The converter control unit (Fig. 2) contains a master oscillator 34, the output of which is connected via a trigger 35 and a block 36 of buffer amplifiers with control inputs of keys 3-6 of the main inverter 1. In addition, the output of the master oscillator 34 is connected via frequency generator 37 to the input of a binary counter 38, the outputs of which are connected to the address inputs of a programmable permanent storage device 39 having six outputs 40-45. Last through logical elements NOT 46-51,

2-2IL-2ILI 52 and 53, 3-ZI-2ILI 54-57, HE 58-63 and 2I 6A-67 are connected to the inputs of the block 36 buffer amplifiers, the outputs of which are connected to the control inputs of the keys 7-10. Of the auxiliary inverter and keys 26-33 AC. Moreover, the output numbers of the block 36 buffer amplifiers correspond to the numbers of the keys to the control inputs of which these outputs are connected.

Transistors or thyristors with reverse diodes can be used as keys for 3–10 single-phase inverters, and triacs, counter-parallel-connected thyristors or transistors with series-connected diodes, transistors included in constant diagonals can be used as alternating current keys 26–33. current diode bridges.

In FIG. 3, the diagrams represent the pulse shapes at the outputs of the following elements: 68 — master oscillator 69 and 70 — trigger 35 (direct and invariant signals, which are control for keys 3-6, respectively); 71 - main transformer 11, 72 - frequency divider 37; 73-76 — Elements 52, 58, 53, and 59 (key control pulses 7, 10, 8, 9, respectively); 77 - auxiliary transformer 12; 78-85 elements 54.64, 55, 65, 56, 66, 57, 67 (key control pulses, respectively, 2633); 86 — converter (output linear voltage

) The device works as follows.

In order to improve the shape of the output voltage curve in the converter, the pulse-amplitude modulation of the output voltage is performed, and for reducing the weight and size of the transformers, the constant voltage is converted to an alternating voltage at a high intermediate frequency.

The master oscillator 34 (Fig. 2) generates a sequence of pulses 68 (Fig. 3), which is fed to the input of the trigger 35. The signals 69 and 70 of the direct and inverse outputs of the trigger 35 are amplified by the block 35 of the buffer amplifiers and are fed respectively to the control inputs of the keys 3 -6 inverter 1. In addition, the frequency of the master oscillator 34 is divided by divider 37 and fed to the input of binary counter 38 with a conversion factor of equal, for example, 18.

From the outputs of the counter 38, the signals arrive at the address inputs of the programmable permanent storage device 39, the logical states of the outputs 40-45 of which, depending on the address code, are presented in the table (Fig. 4). They allow or prohibit the passage of signals 69 and 70 from the direct and inverse outputs of flip-flop 35 to the inputs of block 36. Moreover, the logical zero level at the input of block 36 ensures the closed state of the power switch, and the logical unit level is open. As a result, the necessary pulse sequences are generated to control the power switches 7-10 of the auxiliary inverter 2 and the alternator current keys 2633. The output voltage of converter 86 can be split into 9 equal intervals.

In the first interval, in accordance with the table, the logical states of the outputs 40-45 of element 39, respectively, have the following values 111110. In this case, from outputs 40-43, the signals of the logical unit are fed to the inputs of elements 52-54, allowing the passage of pulses 69 from the direct output of the trigger 35 to the inputs of block 36. The output signals 73, 75, 78 of elements 52-54 are amplified by block 36 and fed to the control inputs of power switches 7, 8 and 26. In addition, these pulses are inverted by elements 58-60, output signals 74, 76 and 79 which come through the block 36 to the control inputs keys 10, 9 and 27 respectively. From the output 43 of the element 39, the signal of logical units is inverted by the element 49 and locks the elements 55 and 65, prohibiting the passage of pulses 80 and 81 to the control inputs of the keys 28 and 29. From the output 45, the signal of the logical zero goes to the inputs of the elements 51, 56 and 66. When this, elements 56 and 66 are locked and the passage of pulses is stopped. 82 and 83 to the control inputs of the keys 30 and 31. The output signal of the element 51 corresponding to the level of the logical unit, unlocks the elements 57 and 67, r allowing pulses to pass from the 51 direct output of the trigger 35 through the element 57 to one of the inputs of the block 36 The output signal 84 of the element 57 is supplied through block 36 to the control input of the key 32 and through an inverter 63 to the input of the element 67. The output signal 85 of this element is amplified by the block 36 and fed to the control input of the key 33. At the following intervals, the formation of control pulses power keys are transformed The drives are similar in accordance with the diagrams 68-86 (Fig; 3) and the truth table (Fig. 4) of the state of the element 39. As a result of the operation of inverters 1 and 2, the voltages 71 and 77 are formed on the windings of the transformers 11 and 12. The shape of the linear output converter 86 is shown in FIG. 3. It is characterized by a constant difference in the amplitudes of the two adjacent stages and a duration of the average stage equal. To obtain a voltage with the indicated amplitudes of the voltage steps in sections 1821 (Ojjig - Upn) of the secondary windings of the main transformer and on the secondary windings 22-25 (UAJ 025 of the auxiliary transformer 12 must be associated with the amplitudes of the steps of the output linear voltage of the converter (11 -U, Fig. 3) as follows,., Og2-- 053 4 0C 5 1 In addition, it should be noted that for the amplitudes of the steps, the following equalities U, tUi U2, U, 4U, j-tl3, U2 + U2 - (J4In accordance with the received division factor of divider 37, equal to 4, the interval of each step the output voltage of the converter can be divided into 4 subintervals, corresponding to the half-period of operation of transformers 11 and 12. In the first subinterval of the first interval, alternating current switches 26 and 32 are closed (diagrams 78 and 84, Fig. 3). To the output pins A and B of the converter, the voltage difference between section 20 and winding 23 is applied, equal to UAb-Uc2o Uo23 U2-U, U ,, 06 to pins B and C through key 32, the sum of the voltages of sections 20 and 21 ((, to conclusions C and A UcA - LI e UBcb- (UrU4) U3. On the second subinterval of the first interval, the polarity of the voltages on the windings of the main and auxiliary transformers changes (diagrams 71 and 77), closing the switches 27 and 33. To terminals A and B, apply the voltage difference of section 19 and winding 22 A6 U ,, -Uoa2 Ua-U, .U, to pins B and .C, the sum of the stresses of sections 18 and 19 UBc 4bc, (., (Ui U2b-U4, to pins C and A isAA-- lv iesb- (, t. E. The values of the linear voltages remain the same. Later on, in the first interval, the operation of the keys is repeated for odd and even subintervals, respectively, and the first positive, the fourth is negative and the third is positive with the linear voltage Ud, UQ and respectively.Key 26 and 32 are closed again in the first interval of the second interval, but the voltage 77 on the secondary windings of the auxiliary transformer 12 is absent during the entire interval. and B applies a voltage of section 20, equal to terminals B and C via key 32 - the sum of the voltages of sections 20 and 21, to you-. waters C and A l cA - Ufte Ugcl-lUrUO-Uj. On the second subinterval of the second interval, the keys 27 and 33 are closed. To terminals A and B, a voltage of section 19 is applied, equal to AB Uciq - U ,, To terminals B and C is the sum of the voltage of sections 18 and 19,) - ( a2 +,

to conclusions C and A of cr-4U g + Ugcl 4U, -U4) -Ui.

later, in the second interval, the converter operation is repeated for odd and even subintervals, respectively, and the second positive, fourth negative and second positive linear voltage levels U, U o and Uj are formed; In the following intervals, the converter operates similarly in accordance with pulse diagrams controlling the keys and voltage forms on the windings of transformers 11 and 12. As a result of the operation of the converter, a three-phase four-stage voltage 86 is formed at its output.

Connecting any branch of the circuit using AC switches allows current to flow in two directions and constant: In the potential difference of the phases during each interval. This determines the efficiency of the converter at any load power factor with a constant output voltage curve. Adjusting the output frequency of the converter can be done by changing the division ratio of the divider 37 at a constant frequency of inverters 1 and 2 and transformers 11 and 12, which favorably affects the weight and size characteristics of the converter.

The proposed converter has a smaller mass and size as compared with the known one, since the transformer, the latter, operates at frequencies 3 and 6 times the converter output frequency, and the transformers of the proposed device at any high frequency. Calculations show that when the output frequency of the converter is below 25 Hz, the transformers of the proposed converter have 3 or more times less mass and dimensions.

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Claims (1)

The DC / DC converter is in three-phase AC with the output terminals of the transducer of the opposite arm, and the intermediate terminal of each half-winding is connected through the secondary winding of the auxiliary transformer and the AC key to the output terminal of the converter of this arm. Φυΐΐ 1 I 12511)