SU1410243A1 - D.c. to three-phase quasisine voltage converter - Google Patents

Abstract

The invention relates to electrical engineering, in particular to converter equipment. The goal is to increase the quality of the output voltage by reducing the hormone ratio. The converter contains the main and auxiliary single-phase inverters, made on the keys 1-4 and 5-8, loaded on the main 9 and auxiliary 10 transformers. The ends of the secondary winding of the main 9 transformer are connected via alternating current keys 14-19, and its intermediate tap through the secondary winding 13 of the auxiliary 10 transformer and alternating current keys 20-22 are connected to the output terminals of the converter. The specified intermediate tap divides the secondary winding of the main transformer 9 according to the number of turns at a ratio of 2: 3, and the transformation ratios of the main 9 and auxiliary 10 transformers relate to each other as 5: 1. The voltages of the secondary windings of the main 9 and auxiliary 10 transformers are algebraically summed. Through alternating current switches 14-22, these windings are connected in a certain sequence to the output outputs of the converter, where a three-phase multi-stage voltage is formed, which is close in shape to a sinusoidal voltage. 4 il. S

Description

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The invention relates to electrical engineering and can be used in the secondary power supply system It electric drive to convert a constant voltage into a three-phase alternating voltage with a cryo-voltage close to sinusoidal, I The purpose of the invention is to increase the output voltage by jiec fBa by reducing the harmonics .

FIG. 1. shows a schematic diagram of the power part of the converter; in fig. 2 is a schematic diagram of a converter control system; in fig. 3 shows diagrams explaining the principle of the formation of pulses controlling the power switches of the transducer; in fig. 4 is a truth table of a programmable read-only memory. I The converter contains the main | and auxiliary single-phase inverters, | executed respectively on Keys 1-4 and 5-8. The outputs of the inverters | are loaded on the primary windings of the main 9 and auxiliary 10 transformers. Sections 11, 12 of the secondary winding of the main transformer 9 and the secondary winding 13 of the auxiliary transformer. 10 are interconnected and via AC keys 14-22 with output terminals A, B, C of the converter. As keys 1-8 of inverters, transistors or thyristors with reverse diodes can be used, and as keys 14-22 of alternating current - seven hundred; ry, anti-parallel connected thyristors or transistors with sequentially; diodes, included in the diagonal DC diode bridges.

The converter control unit contains a master oscillator 23, the output of which is connected via a trigger 24 and a buffer amplifier block 25 with control inputs of inverter keys 1-4. In addition, the output of the master oscillator 23 is connected to the input of a binary counter 26 of pulses loaded on the address inputs of the programmable permanent memory 27 ,. performed, for example on a chip 155 RES. The codes 28-38 of the latter are connected via the logical elements 39-40 of HE and block 25 with the control inputs of the keys 5-8 and 14-22 of the converter. But

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the measure of the outputs of block 25 correspond to the numbers of the keys to which they are connected.

FIG. 3, diagrams 41-59 represent the pulse shapes at the outputs of the following elements: 41 — master oscillator 23, 42-43 — direct and inverse outputs of the trigger 24 (control pulses of 1-4 inverters), 44-47 — at outputs 28 29 devices 21 and outputs of elements 39, 40 (control pulses with inverter keys 5-8), 48-49 - transformers 9, 10, 50-58 - at outputs 30-38 of device 27 (control pulses of keys 14-22), 59 - converter (form of output phase voltage id).

The device works in a continuous manner.

The master oscillator 23 (Fig. 2) generates a sequence of pulses 41 (Fig. 3), which is fed to the input of the trigger 24 and the input of the binary counter 26, with a factor ||) conversion factor of 15. Signals 42, 43 of the forward and inverse outputs of the trigger 24 are amplified by a block 25 buffer amplifier and fed to the control inputs of the keys 1-4 of the inverter. From the outputs of the counter 26, the pulses arrive at the address inputs of the programmable read-only memory 27, the logical states of the outputs 28-38 of which, depending on the address code, are shown in FIG. 4. Moreover, the level of logical zero at the input of block 25 provides the closed state of the power switch of the converter, and the level of the logical unit is open. As a result, the necessary sequences of 43-47, 50-58 pulses of control of the power switches of the converter are formed. The half-period of the output voltage of the 59 converter can be divided into fifteen

equal intervals. one

In the first interval, the signal from the master oscillator 23, the counter 26 is set to the initial state 00000, to which the code 10001001100 corresponds to all, and the device 27 (Fig. 4). Consequently, in addition to the keys 1, 4, controlled by the signals from the master oscillator 23, the power switches 5, 16, 19, 20 are unlocked from the outputs 28, 32, 35, 36 by signals of logical units. In addition, from the exit

29 of the device 27, the logical zero signal is inverted by the element 40 and unlocks the power klvdch 8.

In the second interval, from the outputs 28, 33, 34, 36 by signals of logic one; the keys 5, 17, 18, 20 are unlocked. The inverted signal from output 29 remains, the key 8 is unlocked. The control pulses are generated at the next intervals in the same way as described in Figs 41-58 of FIG. 3 and the truth table of the device 27 (Fig. 4). As a result of the operation of the inverters, the voltages 48, 49 (Fig. 3) form on the windings of the transformer 9, 10, and at the load phase, the star is connected to an eight-step voltage 59. The amplitude of the steps from the first to the eighth

and 5U „„ 7U 8U of the latter are equal to t, U, -g, 2U, -, -g

5, t 10U „

Zi, o where and is the amplitude

stress

on the winding 13 of the auxiliary transformer 10. In this case, the voltage on sections 11, 12 of the main transformer 9 is respectively 2U and 3U, i.e. the intermediate tap of the secondary winding of the main transformer 9 divides it by the number of turns in the ratio 2: 3, and the transformation ratios of the main and auxiliary transformers are related to each other as 5: 1. The half-period of the output voltage 59 can be divided into 15 equal intervals.

In the first interval, the keys 1, 4, 5, 8, 16, 19, 20 are closed (diagrams 42, 44, 47, 52, 55, 56). In this case, through closed keys 20,, 16, the output pins A, B are applied to the output

Claims (1)

Invention Formula into a three-phase quasi-sinusoidal voltage, containing the main and auxiliary single-phase inverters, loaded, respectively, on the primary voltages of section 11 and winding 13, equal to zi. The sum of the voltages of sections 11, 12 is equal to 5U, and the terminals C, A through keys of 19, 20 - the difference of the voltages of sections 12 and winding 13 are equal to 2U - to the terminals B, C through the keys 45. . In this case, the phase voltage of the 50th and auxiliary transformer of the load connected by a star ry, the ends of the secondary winding of the first one are respectively: of which are connected via keys AC to each of the output- and ULI-GUYA. Zu-2u UBc-IHAt. converters, and its 55 intermediate tap is connected to these 7U outputs through the secondary winding of the auxiliary transformer, i.e. a first positive is formed, pa, characterized in that the pole is negative, n the one is positive, in order to increase the quality of the output. : 5u-z y: | y, (, phase voltage step ST. U. Uc In the second interval, the keys 2, 3, 5, 8, 17, 18, 20 are closed, the polarity of the voltages on the windings of the transformer 9 changes. The sum of the voltages of section 12 and the windings 13 is applied to the terminals A, B through the keys 20, 17, equal to 4U, k, t C and B via keys 18, 17 - sum of voltages of sections 11, 12, equal to 5U, to conclusions C, A through keys 18, 2b - difference of voltages of sections 11 and winding 13, equal to U. Phase the stresses become equal to U, .- 3U, 2U, i.e. a second positive, seventh negative, and fourth positive phase voltage phase are formed. At the following intervals, the operation of the converter occurs as described in accordance with diagrams 41-58, FIG. 3 and the truth table of the device 27 (Fig. 4). Connecting any branch of the circuit using controlled keys with double-sided conductivity allows current to flow in two voltage and constant phase potential difference during each interval. This determines the efficiency of the converter at any load power factor with a constant output voltage curve. The described converter allows the shaper to form an eight-step output voltage curve without complicating the converter circuit, instead of the six-step curve in the prototype. Invention Formula Three-phase quasi-sinusoidal voltage, containing the main and auxiliary single-phase inverters, loaded on the base respectively. The converter of the constant voltage and auxiliary transformers, the ends of the secondary winding .first of which are connected via keys 514102436  voltage by reducing the ratio of 2: 3., and the harmonic coefficients, intermediate transformation of the main and auxiliary output of the secondary winding of the main transformer relate to the transformer divides it by the number of vit-like between 5: 1. Have 1L 2,3 7 M L. 29 50 five/ 32 33 M 35 F IL Sv five -5 -6 -7 -в -1 -iS -f6 -17 -16 -f9 -20 -21 .22 sriе.2 (rigz