SU1529458A1 - Code converter - Google Patents

Abstract

The invention relates to automation, information-measuring and computer technology. The aim of the invention is to extend the class of tasks to be solved by providing conversion of a binary code to a code with a base √2. In the code converter containing register 1 and multiplication unit 2, the group of elements OR 3, the element AND-NOT 4, the expander 5, the output register 6 are added, and the expander 5 contains the first and second groups of elements I. 1 zpf- ly, 2 Il.

Description

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the next

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The invention relates to automation, information-measuring and computer technology and can be used to convert binary code into code, with base v2.

The aim of the invention is to expand the class of tasks to be solved by providing a conversion to code with a base VJ.

Fig, 1 shows the structural scheme of the proposed Converter; figure 2 is a functional diagram of the extender (5) about

The converter (fig.)) Contains the register 1, block 2 multiplication (CU). a group of elements OR 3, an element .NI-A, expander 5, output register 6, information input 7 of converters, input 8 of information output, inputs of the first 9 and second 10 operands of the multiplication unit 2, input 11 of the multiplication unit constant, input 12 control of the converter, inputs of the lower 13 and higher 14 bits of the expander, nepvy 15 and second 16 inputs of the converter mode, first 17 and second 18 inputs of information, output 19 of the former “

The extender 5 (Fig.2) contains the first group of elements And 20, the second group of elements And 21. Each of the groups of elements And 20, 21 contains four elements

The construction of the proposed converter is based on the following.

The number N, represented 2n times, in a single code with a base - / 2, has the form

2n-t

,,, (/ 2) -.а, „., (/ 2)

Ih-z

-ba (V2) ...- t-a (V2)% a, (/ 2) +

+ ao (V2)

(one)

V The weights of the code bits with a base 2 constitute a sequence

. „J6 / 2, 16, 8 V2, 8, 4/2, 4,

2/2, 2, - / 2, 1 (2)

From expression (2) it follows that even degrees are weights of bits of a binary code, and odd ones are weights of a binary code multiplied by

With this in mind, the code of the number N, represented by the expression (1), we write in the form

- / 2 Z: a.2 tg s

gp-g

+ Z a-2 J-

J /

(3)

where a; and. e i O, 1} and are digits of a binary-coded number system with a base of / 2, and i, j for 2n-digit numbers take on the values:

i e G1,3,5, ..., 2n-1 I J e 0,2,)

5 0 5

0

five

0

five

0

,

The first member of formula (3) is the sum of the odd bits of the NJ code and the second is the sum of the even bits of the same code. Expression (3) contains two binary parts

An arbitrary number N in the number system with a base seems ambiguous, since it can be arbitrarily divided into two numbers N and. In this case, the number N can be represented in a code with a base / 2 in odd bits, and N in even numbers, and vice versa. The number of ways to divide the number N into N and N is determined by the bit grid of the original number

Let us consider three variants of such a representation, each of which has its own transformation mode "

Option 1. The representation of the initial number N is only for even bits, while the odd bits are filled with zeros, i.e. / see formula (3))

(one)

Example 1-,. 101 01000C.

Option 2 "Representation of the number N only for odd bits, while even bits are filled with zeros, i.e." a; 0 (see formula (3)).

Example 2. (1 Yu. ".4000 (, -949 (,,,.

The conversion algorithm is as follows. The initial number N, represented in binary code according to formula (3), is multiplied by the binary equivalent of the number t2, after which the result of the product is shifted by one bit towards the lower bits. This corresponds to a record of the result of the product in the corresponding bits. Then we expand the result obtained, i.e., after each discharge of the product, there will be a discharge containing zero, and the total number of bits will be doubled.

p. N.5, .. 1000 ,,,

101 (g, s 1 11

Applied A-949 (10).

/ 2-1-01 101 (11

/ 2-N (t, 1 -01101 (, 00001 (1 ,.

After shifting one bit to the right: 11-1000001 (71.

After expanding the result: 1010 1,000,000,00010 (Yi).

Thus, :: i 1 010-1000 u) "

Option 3, Representation of the number N for even and odd bits together. The conversion algorithm is as follows:

N ,, N (/ 2-1.) (V2 + 1) M (V2-H) N (yj ,, (4)

where - () N 0,414,

That “the initial number N, presented

Section 1 through the groups of elements OR 3 steps into the input 13 of the expander 5, its spatial expansion occurs (example:) 010001). From the output of the expander 5, this code is written to the output register 6, and then ptoodes input 19 of the converter in the presence of a control signal at input 17 "

Convert binary code to code with a base - / 2 for odd bits,

In the initial state, the first 5 and second 16 inputs of the converter mode are supplied with zero control potentials. The binary code of the initial number (101) is entered in register I. With the arrival of the control signal on

ten

in binary code, multiplied by the binary 20 input 8 of the information output is the binary equivalent of the number (-1). Then

The code of the initial number from the output of register 1 enters input 9 of the first rand of block 2 multiplication, after the output of information from register 1 is terminated by inputting 8 n of the left potential to the input. Then the control potentials are fed to the first 15 and second 16 inputs. O and 1 respectively, with the input M con

an extension of the result K is produced, Toe "after each bit of output will be. There is a bit containing zero, and a total 25

 the number of bits doubles. Then we shift the received code by one bit in the direction of the dry bits and add the received code to the code

before the shift. These operations are equivalent to 10 stanta from the output of the AND-NOT 4 foam element multiplying the number by (/ 2-Ü1) (see forwards 1, and at the input of the second one the code of the initial number from the output of the register 1 goes to input 9 of the first operand of block 2 multiply, after which the output of information from register 1 is terminated by applying zero potential to input 8. Then, the control potentials O and 1 are fed to the first 15 and second 16 inputs, respectively, while the input M con 5,)

Mule (4)). at

Example 3. N

V2-1 O Ol 101 (2,

N- (2-1) 101 (g, - O OllOl (J, 10 "00001 (,.

It should be noted that the last three operations of expansion, shift and addition correspond to the operations of representing each digit of the digit with two identical digits, which is realized in the converter.

The proposed Converter works as follows

Consider his work in three modes of

Convert binary code to code with V2 base on even digits.

In the initial state at first

15 and second 16 mode inputs are fed to control potentials 1 and O, respectively. The multiplication unit 2 does not participate in the operation. The binary code of the initial number is entered into register 1. With the arrival of the control signal at the input B of information output, the binary code of the initial number from the output of register 1 through the element groups OR 3 is fed to the input 13 of the expander 5, where its spatial extension (example:) 010001). From the output of the expander 5, this code is written to the output register 6, and then fed to the input 19 of the converter in the presence of a control signal at the input 17 "

Convert binary code to code with a base - / 2 for odd bits,

In the initial state, the first 15 and second 16 inputs of the converter mode are supplied with zero control potentials. The binary code of the initial number (101) is entered in register I. With the arrival of the control signal on

input 8 binary information output

The code of the initial number from the output of register 1 is fed to input 9 of the first operand of block 2 multiplication, after which the output of information from register 1 is stopped by applying zero potential to input 8. Then the control potentials O and 1 are fed to the first 15 and second 16 inputs of the mode, respectively , at the same time, the binary code of the number V2 -1 "0, А14-0-01-01 (the information from inputs 10

and I1 is written into the multiplicable register. With the arrival of the signal at control input 12, the multiplication of co; keeping the multiplier register (1 xOllOl) and multiplier (101) and shifting the result of the product by one bit to the right, after which the output of multiplication unit 2 results in the output (11-100001), 10 at the first output of multiplication unit 2 and O UOOG -

at its second output, which through the group of elements OR 3 and directly go to the inputs 13 and 14 of the expander 5, where the recording into odd bits and expansion occurs (lOlOx

 1000 (У5;), see example 2). From the output of the expander 5, this code is written to the output register 6, and then, with a control signal at input 18, it goes to the output 19 of the transducer.

Converting a binary code to a base with a base of / 2 on even and odd bits together differs in the described mode in that

The first 15 and second 16 inputs of the mode setting are supplied with single control potentials, while the input 11 of the constant from the output of the NAND 4. element is O. The code of the number 2 1.414 O 01101 (i) is written to the multiplicative register. With the arrival of the control signal at control input 12, the multiplication of the register of multiplicand (0-01101) and multiplier (101) occurs, after which the output of multiplication unit 2 results in the output (10-00001), 10 - at the first output of the block 2 multiplications and 00001 - at its second output, which through the group of elements OR 3 and directly go to inputs 13 and 14 of the expander 5, where the recording occurs in even and odd bits, i.e. duplication (1 SOO OOOOOOOOP (, see, example 3). From the output of the expander 5, this code is written into the output register 6, and then, if there are control signals at inputs 17 and 18, is output at output 19, it is converted.

In the general case, the conversion of a binary code into a code with a base V2 can be carried out as follows.

The binary code of the source number is represented as the sum of the binary ko and numbers N, and N2iN Ni + N2. Then the binary code of the number N is entered into register 1, after which it is converted in mode 1. After that, the binary code is entered into register 1

numbers N, and it is transformed in mode 2. As a result of this conversion, output code 6 will contain a code with base V2 of the initial number N, represented by both nL even and odd bits

Claims (2)

Invention Formula 1, The code converter containing the multiplication unit and the register, the output of which is connected to the input of the first operand of the multiplication unit, the bit input of the register is the information input of the converter, input 8 0 five 0 0 five 35 40 45 50 This information is connected to the register entry input, which is based on the fact that, in order to expand the class of solved tasks by providing conversion to the base code / 2, the expander, output register, OR element group and AND element are entered into it. - NOT, the first and second inputs of which are respectively connected to the first and second inputs of the converter mode and the first and second control inputs of the expander, the inputs of the higher bits of which are connected to the outputs of the elements of the OR group, the first and second inputs of which correspond They are connected to the outputs of the register and the outputs of the higher bits of the multiplication unit, the outputs of the lower bits of which are connected to the inputs of the lower bits of the expander, the outputs of which are connected to the discharge inputs of the output register, the first and second control inputs of which are respectively the first and the second inputs of the converter information switching, the information outputs and the input of a constant of which are respectively connected to the outputs of the output register and the input of the second operand of the multiplication unit, the input of which is constant connected to the output of the K-NOT element, the control input of the converter is connected to the control input of the multiplication unit. 2. The converter according to claim 1, characterized in that in it the expander contains the first and second groups of elements AND, the first inputs of which are respectively connected to the first and second control inputs of the expander, the information input of the i-ro extender (... 4p ), where 2n is the number of bits of the input code, is connected to the second inputs jx of the elements AND of the first and second groups, the outputs of which are respectively outputs () ro and 2i-ro extender bits, information inputs from the first to three bits form the input i junior bits extender, and information The inputs from the (2p + 1) -th to 4p bits form the inputs of the higher-order extender bits.