SU1529235A1 - Device for routing messages - Google Patents

Abstract

The invention relates to computing and can be used to organize machine-to-machine exchange in distributed computer complexes and computer networks. The aim of the invention is to increase the capacity of the device in the range of long messages. The goal is achieved by the fact that the device contains an input storage unit 1, a header decoding unit 2, a central storage unit 3, an arithmetic logic unit 4, a firmware control unit 5, a message receiving unit 6, the first and second switching units 7 and 8, unit 9 issuing messages. 2 hp f-ly, 5 ill.

Description

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The invention relates to computing and can be used to organize exchange in distributed computing systems and computer networks.

The purpose of the invention is to increase the capacity of the device in the range of long messages

FIG. 1 is a block diagram of a device for switching messages; FIG. 2 is a block diagram of a message receiving unit; Fig 3 is a block diagram of a block of messages, messages; in FIG. 4, the block diagram of the IC pattern control unit J in FIG. 5 is a block diagram of the arithmetic logic unit.

The device for switching messages (Fig „1) contains an input storage unit 1, a header decryption unit 2, a central storage unit 3, an arithmetic logic unit 4, a microgram control unit 5, a message reception unit 6. The first block 7 to -1 mutate, the second switching unit 8 is a 9-out block, messages, output 10 Data request 5 output 11 Data request, information input 12, output 13. Synchronization of receiving block 6 output 14 of block 6, output 15 of block 7, output 6 of block 8, output 17 Response block 9, the output 18 of the acknowledge signals of block 9, the output 19 of block 9, the first and second e inputs 20 and 21 of data, the first and second control yupsche inputs 22 and 23, yield 24 address of the next microinstruction unit 5, output unit 25 5 26 output unit 4, 1p output unit 27 output unit 28 2 and output 29 of unit 3,

The receiving unit of the message (FIG. 2) consists of a register 30 of the state j of the register 31 of the input register 32 and the synchronization register 33.

The message block (Fig. 3) constitutes the output register 34, the synchronization register 35, the fade register 36, the acknowledge signal register 37 and the status indication register 38.

The microprogram control unit (FIG. 4) contains a read-only memory (ROM) 39, a microinstructor address register 40, a microcommand register 41, an operation code decoder 42 clock generator 43, a time distributor 44 and an output node 45,

Arithmetic logic unit (Fig „5 is made in the form of a switch 46 of the first operand, switch 47 of the second

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operand, register 48 of the first operand, register 49 of the second operand, combinational adder 50 and result register 51.

Block 1 of the input drive is intended for intermediate memorization of codograms (device operation mode 1 — mode of codogram transmission) and control messages (device operation mode 2 — data transfer mode and long messages).

The size of the memory cells of the input storage is determined by the number of memory modules in the row of the storage matrix, the number of memory cells of the storage device is determined by the number of modules in the column Mc1 TRICKS

The header decryption unit 2 is designed to encode information defining the header of the code (device operation mode 1) and the control message (device operation mode 2),

The central storage unit 3 serves for intermediate storage of codograms and control messages in the event that the corresponding output port is occupied.

The arithmetic logic unit 4 performs arithmetic logic conversions determined by the type of operations performed, for example, adding operands or sending one of the operands

The firmware control unit 5 includes a ROM 39 and synchronizes the operation of the device blocks.

The message receiving unit 6 provides for issuing data request signals to the transmitting subscriber at outputs 10 and 11 and receiving data from the subscriber via information input 1.,

The first switching unit 7 provides end-to-end (bypassing the microprogram control unit 5) control of the data flow entering the device 12 "

The second switching unit 8 performs through (bypassing the input storage unit 1 and the central storage unit 3) data transfer between the interacting devices „

Block 9 of the message delivery provides reception of acknowledging signals and response codes from the receiving subscriberj arriving at the inputs 23 and 22, as well as from 5,129,235.

Performs data output to outputs 20 and 21.

The device works in two modes

on whether from

As a result, in the register 40, the address of the microprogram of the address information analysis is set.

1st device operation mode — enumerates from input 1 block 6

As a result, the register 40 sets the address of the microprogram of address information analysis. The microprogram of the analysis you called from the ROM 39

codogram

A feature of this mode is the simultaneous transmission of the control

information encoded in the header - | Q ka 1 from input 25. Read from block

ke codograms and data

The codogram format consists of a header field, which contains the output port number (physical output point) of the device, the transfer command code, the input port number (physical input point) of the device, and a data field that has a fixed size.

The 2nd mode of operation of the device is characteristic 20 (available / unavailable)

It is controlled by the transmission of arrays of data and long messages, the length of which exceeds the length of the codograms. A feature of this mode is the transmission

a control message that the status transmitter to the transmitting subscriber

in the device, a physical pass-through channel between the receiving and transmitting subscribers with the subsequent transfer of data through it.

 The control message is transmitted by JQ as a short codegram and contains the number of the output port of the device, the length of the information block 41 and the number of data blocks transmitted to the subscriber.

Both codograms and control messages are transmitted with intermediate memory in the input and / or central storage devices of the device. Data arrays and long messages are transmitted directly from the transmitting subscriber's RAM to the receiving subscriber's RAM via the pass-through channel organized in. device.

The operation of the device in the 1st mode is as follows.

From the transmitting device, the input information 12 is fed to the address information, accompanied by a clock signal, which are respectively recorded in the registers, 50 32 and 33 of block 6

The incoming address contains the code of the zone number of the input drive required for storing the codegram. The output 13 of the register 33 is inputted to the input of the register 40 of the microprogram control unit 5, the output 14 of the register 32 is inputted to the input of the switch 46 of the first operand of the unit 4.

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In this case, the status code from the output of the register 51 of the result of block 4 from output 26 is written to the register 30 of the block 6. In the case of matching the status code of the bladder zone of the accumulator, the request code is written to the request register 31 of block 6, and the outputs 10 and 11 of block 6 After that, the control is transmitted to the codegram receiving microprogram In response to the request, the transmitting subscriber writes the first word the gram code to the register 32, the sync signal to the register 33, and the sync signal sets the O register to the 32 register request. By receiving receive firmware, the word from register 32 is written to the switch of the first operative 46 of block 4, and without conversion in block 4, output 26 is written to the cell of the selected zone of input drive 1. After this, the receive firmware gives output 6 to register 31 on output 26 of block 4, the code of the request for the next cogramme number The number of cycles of reception is constant and corresponds to a fixed size of the codogram. and receipt unit 6 is provided in the video code state (completion of receiving code).

l state word by input to output 24 of the corresponding address and read signals issued to the input block state word output 27 and the write signal produced by: output node 45 of block 5, inserts the word code into switch 47 of the second operand of block 4, in which analyzes the status word and determines the availability of the input storage required by the subscriber

Depending on the state of the zone

a status code that is issued to the sender. For this purpose, the analysis firmware transfers control of the information output firmware.

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In this case, the status code from the output register 51 of block 4 from output 26 is written to register 30 of block 6. If the free zone status code corresponds to the accumulator, the request code is written to block 31 of the request 6 and the outputs 10 and 11 of block 6 are activated. After that, the control is transferred to the codegram receive microprogram. In response to the request, the transmitting subscriber, at input 12, writes the first codogram word, and to the register 33, a synchronization signal. At the same time, the sync signal sets the O register of request 3 to the O register. the reception microprogram board overwrites a word from register 32 to the switch of the first opamp 46 of block 4, which without conversion in block 4 on output 26 is written to the cell of the selected zone of input drive 1. After that, the receive microprogram returns to register 31 of block 6 on output 26 of block 4 request code of the next codogram word The number of receive cycles is constant and corresponds to a fixed size of the codogram. Upon completion of receiving the codogram in block 1 of the input accumulator, the sending subscriber leaves the register 30 s. hundred audio unit 6 is provided in the receipt code state VIDEO (completion of receiving code).

; D Servicing of the codogram received in block 1 is performed by sampling a header, the code of which from output 27 of block 1 goes to block 2 of decrypting headers ,,:: Output 28 of block 2 is input to input. register 40 addresses of microinstructions of block 5j, depending on the informant, contained in the header of the codegram, control is transferred to one or another branch of the service microprogram. After decoding the output port number, the service microprogram performs a rewrite on output 19 of the register 38 code indicating the state of block 9 to block 4 and compares it with the code number of the output port to which the codec 1 mao is intended. If the output port is occupied, then the codogram is rewritten without conversion from block 1 of the input drive on output 27 to the block 4, with the result register 51 is output without conversion is input to the central unit 3 and the accumulator 3 of the control signals coming from the output unit 25 5 performs recording overheads | In unit 3 the central accumulator. Recorded in central block 3

A feed is put at the end of the turn of turn of the callograms to this output port

Forwarding codogram; carried out through the arithmetic logic unit 4 o If the output port is available

then in block A. the comparison of the ranks of the codogram recorded in the input drive 1 and the codogram standing at the beginning of the queue in block 3 of the central accumulator with the comparison of the ranks is carried out as follows. In block 4, the code of the rank of the cogram of the waiting pattern in the central the rank code entered into register 49. In the rank of the message received in the input accumulator, the signals of the rank code 50 are compared to block 4 from block 5 of the microprogram control on output 25 to the combinational adder 50 The result of which can have two meanings: V A, AoV code comparison result is recorded in the result register 51 and the output 26 is supplied to the address register 40 micro rokomand. In the first state of the comparison result, a rank-A message is output to the output port, and if the second one is received.

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5 rum - communicating rank B, Depending on the result of the codogram comparison, the output is carried out either from the input storage unit at output 27 via switch 47 of the second operand, combinational adder 50 (word passes through without conversion) and from the output of reg. the result of output 26, which is preliminarily connected by block 8 to the input of block 9, or from the central storage unit through block 4, switching unit 8, the next word is written to the output register 34 of the 9o unit after issuing the codogram. The frame recorded in the input storage unit is rewritten to the central storage unit.

A codogram is sent out word by word on the cipogram firmware test. This is done as follows.

The program for issuing a codogram seizes the port by outputting at the output 26 of the register 51 of the block 4 the sign of occupancy to the register 38 of the block 9 "The address of the first word of the codogram is selected from the ROM and depends on the location of the codogram (input drive / central drive) output

24 either to the input of block 1, or to the input of block 3, the clocking pulses, which are used to collect information at a specified address, are received from the output node 45 from the output

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The selected word from any Accumulator goes to block 4, from the output of which it is entered into the output register of block 9 without conversion, according to the standard, the signal is transferred to register 35 of block 9. At the same time, outputs 20 and 21 are activated. The receiving subscriber reads from register 34 In block 9 and output 22, the corresponding register bit 35 and 1 is set to O, the corresponding register bit 37,

The output of register 37 (output 18) is input to register 40 of the address of microinstructions of block 5, the set code in register 37, affecting the input of register 40, initiates the cycle of issuing the next word codogram

After the end of the codogram, the firmware removes the sign. port in register 38.

Consider the operation of the device in the second mode.

From the transmitting subscriber, the input information 12 is sent to the input 12, which determines the type and zone number of the input memory for storing the control message. The memorization of control messages and their maintenance are analogous to the maintenance of codograms. The difference between the two is that there is no control message; . data field with,

After issuing a control message to the receiving subscriber, the output port remains occupied and control is transferred to the subscriber response analysis firmware about the receiving subscriber, having received the control message from output 21, analyzes the transmission parameters. The subscriber's response can be either positive or negative. When the response is generated, the receiving subscriber activates the control and acknowledgment inputs 22 and 23, and the response code is written to the register 36 of the block 9, and the acknowledgment signal is written to the register 37, which is synchronous with the response code

From the output 18 of the register 37, the acknowledgment signal arrives at the register 40 of block 5, the response code from output 17 passes to the input of the switch 46 of block 4, the analysis software with the arrival of the acknowledge signal receives the block 4 from output 17 of the response code, the response code is analyzed

Based on the result of the response analysis, a status code is generated which, from output 26 of block 4 to input of switching unit 7 and from output of block 7 to output 15, is entered into register 30 of block 6. If the answer of the receiving subscriber is positive, then along with the status code a request code is issued, which is written to register 31 of block 6 "

This activates the outputs 10 and

The next step of the microprogram is to issue in position 7 and 8 of the switching from the output 26 the position number of the codes 15 and 16 to connect the latter with the inputs of the blocks 6 and 9o. From this moment on, the device has a pass-through physical channel between the input and output ports of the device. communication determined by the mutual coherence of the transmission information parameters, and control is transferred

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the microprogram scanning the receipt code expected from the receiving subscriber.

The synchronizing signal and the word passing through the input 12 to the block 6 are transited through the switching block 8 and from the output 16 are written respectively to the registers 35 and 34 of the block 9 above. In the case of receiving a word, the receiving subscriber generates an acknowledgment signal and outputs it to input 23, this signal is set in register 35 and register 1, register 37, this activates the output 18 of block 9, which is connected to the input of block 7, information from the input 15 of which is fed to the input of block 6 and is written to the register 31, wherein the transmitting subscriber receives the request signal of the next data word.

Having received an informational message intended for it or an array of data, the receiving subscriber stops to transmit the acknowledging signals to the input 23 and outputs to the input 22 a receipt receipt receipt code.

The firmware waiting for the receipt code, producing it, sends the code, analyzing the code, connecting the output 17 using the switching unit 7 to the input of the unit 6 and receiving information about the completion of the transmission, which is written to the register 30 and outputting to the sending subscriber. After this, the firmware using block 8 disables output 16 from input of block 9 and removes the sign of the busy output port in register 38.

Claims (1)

Invention Formula 1, A device for switching messages containing an input storage unit, a header decryption unit, a central storage unit, a firmware control unit, an arithmetic logic unit, the output of which is connected to the input. Result of the operation of the Microprogramming control, the output of which is connected to the control input of the arithmetic logic block, central storage unit and input storage unit, the output of which is connected to the first information input of the arithmetic logic unit and the input of the decryption unit agolovkov, whose output is connected to the input of the header block mikg program control, output The address of the next microcommand is connected to the address inputs of blocks input storage and central. storage device whose output is connected to I distinguish BJ in the second information input of the arithmetic logic unit in order to increase the throughput of the device in the long message area, the message receiving unit is entered into the first switching unit, the second switching unit and the message issuing unit whose first output is connected to the input - the acknowledgment signals of the first switching unit and the microprogram control unit to the output of which is connected to the first control inputs of the message receiving unit, the first switching unit ;, the second switching unit and the control input of the message delivery unit, the output of which Response is connected to the same inputs of the arithmetic logic unit and the first switching unit 5 whose output is connected to the second control input of the message receiving unit j whose output is connected to the synchronization input of the reception of the microprogrammed control unit of the second control The input of the arithmetic logic unit is connected to the output of the operand of the message receiving block whose first information input is connected to the information input of the device and to the information input m of the second switching unit, output-: the flow of which was created with the second information input of the output unit communicating 1-SHY5 whose output is connected to the input of the state of the arithmetic logic unit, -the output of which is connected to the second-information inputs of the message output unit, the second switching unit ,, first switching unit, blocks, receiving messages in the first and second outputs Request data of the message receiving block are connected to the same outputs of the device 5; the first and second control inputs of the device are connected Neggi respectively with the first n the inputs of the message issuing unit j the first and the second data outputs of which are the data outputs of the device 2. The device according to claim 1, is that the receiving unit Si  , five 0 i messages contains the synchronization register, the status register, the input register, the request register, the Sync and Write-read inputs which form the first control input of the block, the information input of the block is connected to the information inputs of the synchronization register, the input register, with the first information input of the request register, vspod register synchronization is a sync of block reception, the second control input of the block is connected to the write-read register of the request register and the status register, the outputs of which are the first and the second unit outputs a data request, a second data input unit is connected to a second information input and information request register WMOs home register state output register input is the output block of the operand 3 „Device 1 in accordance with 1, the order of which is that the message issuing unit contains a synchronization register j an output register, a response register ,, an acknowledge signal register, a status indication register, the Synchronization and Record-reading inputs of which form a control input blo ka, the first information input of the block is connected to the first information inputs of the synchronization register and the output register, the second information input of the block is connected to. the second information outputs of the synchronization register and the output register, with the information input of the status indication register p whose output is the output of the block, the first input. the block is connected to the information input of the register of the acknowledge signals, with the third information input of the synchronization register, the second input of the block is connected to the information input of the response register, whose output is - output of the block response, the output of the register of acknowledgment signals synchronization register output owner -. The output of the block synchronization output, the output of the output register is the output of the data block. "T 17 / V one 18 ii9 JmStoifa f QiaSiOKo9 (K5 / 10kam 1,5,5,6,1,8,3) Oefmoit