JPS644385B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer method between each control device in a distributed control system, and in particular to a method for transmitting auxiliary data such as periodic data or failure-related data between each control device in a distributed control system. Regarding the transfer method.

FIG. 1 is a block diagram of a conventional distributed control system. Conventionally, in this type of system, the transfer of auxiliary data required a large number of signal lines connecting each interface device, as shown in FIG. In FIG. 1, n+1 control devices 10
0,101,~,10n and these control devices 10
n+ attached to each of 0, 101, ~, 10n
one interface device 110, 111,
~, 11n are each control device 100, 101, ~,
A main bus 1 for transmitting data between the interface devices 110, 111, to 11n when signals are transmitted and received between the interface devices 110, 111, and 11n.
20 and a data bus 121 for transmitting periodic data or auxiliary data such as fault-related data between the control devices 100, 101, -, 10n, forming a distributed control system. There is. Each control device 100, 101, ~, 10n
The data required between the two is sent from the control device that sends the data to the register in the interface device attached to that control device. The interface device on the sending side transfers data via the main bus 120 or the data bus 121 to the interface device attached to the control device on the receiving side. The control device on the receiving side can process the data sent from another control device by taking in the data transferred to the attached interface device. Main bus 120 and data bus 121
requires a large number of signal lines, and if the number of signal lines is increased in consideration of traffic volume or safety, the interface devices 110, 111, -, 1
1n requires a large number of terminals on the package used, and these interface devices 11
When the distance between 0, 111, and 11n is long, there is a problem that wiring route setting of the signal line becomes complicated.

The object of the present invention is to eliminate the above-mentioned drawbacks, and to utilize some of the controlled units controlled by a specific control device in a distributed control system.
In order to provide a data transfer system that has the same functions as conventional ones, for example, in the case of a distributed control type time division electronic exchange, the time division electronic exchange is used as a means for exchanging auxiliary data between control devices. By using a time division communication path switch, it also has the functions of conventional data transfer methods, making it economical and stable in operation.In addition, the number of signal lines is reduced and the complexity of equipment wiring is eliminated. The object of the present invention is to provide a data transfer method between control devices in a distributed control system.

In order to achieve the above object, the data transfer method of the present invention is a means for exchanging some of the data sent and received between interface devices attached to each control device in a distributed control system. Data exchange between each interface device is performed via a data bus connected to each interface device and its controlled unit, using some of the controlled units controlled by a specific control device. , is characterized in that data is transferred via the controlled unit. The purpose of this is to reduce the number of signal lines connecting each interface device using controlled units in a distributed control system compared to a conventional system, and at the same time The purpose of this system is to provide the same functions as the data bus in the system.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the invention.
In FIG. 2, n+1 control devices 200, 210, . , 211, ~, 2n1, and each interface device 201, 211, ~,
Main bus 300 and data bus 3 between 2n1
01,302. main bus 30
0 is used to transmit data related to the transmission and reception of signals between the control devices 200, 210, ..., 2n0 that occur in the process of call processing by the control devices 200, 210, ..., 2n0 as exchanges, and the data Buses 301, 302 are each control device 200, 21
0, ~, 2n0, or each interface device 201, 211, ~, 2
It is used to transmit necessary data between n1 and is used in a time-division manner in the same way as a time-division communication path. The interface devices 201, 211, . . . , 2n1 are shift registers 203, 213, . Shift registers 202, 212, 2n2 and interface devices 201, 211, .
~, 2n2 and 203, 213, ~, counters 205, 215, ~, for operating 2n3;
2n5, decoders 206, 216, ~, 2n6, and gates 204, 214, ~, 2n4, and bus transceivers 209, 219, ~, 2n9 for exchanging data using the main bus 300.
and by exchanging data via the main bus 300,
Interface devices 201, 211, ~, 2n1
Main bus control units 208, 218,
~,2n8 and selectors 207, 217, ~,2
n7. In addition, the time division communication path switch 305 is shown for the M1 stage.
Interface devices 201, 211, ~, 2n1
Memory 306 and memory 30 that store data between
Memory 307 storing address information of No. 6
, a counter 309 that determines the address of the memory 307, and a decoder 308. The time-division channel switch 305 in the M1 stage is a time-division channel switch that switches the time slot of the data bus 301 to an arbitrary time slot of the data bus 302 as shown in FIG. 2, and specifically, as shown in FIG. It operates on the principle shown in . That is, referring to FIG. 3, the time division communication path switch 305 uses a communication memory 400 (corresponding to the memory 306 in FIG. 2) that stores data to be exchanged with the other party.
, a control memory 401 (corresponding to the memory 307 in FIG. 2) that stores address data specifying the address (write address or read address) of the call memory 400, and a control memory 401 (corresponding to the memory 307 in FIG. 2) for sequentially writing or reading data to the call memory 400. Address data of the control memory 401 (write address data W ₀ ~ or read address data R ₀
~) Sequential address counter 4
02 (corresponding to the counter 309 in FIG. 2) and an address decoder 403 (corresponding to the decoder 308 in FIG. 2), and the control device 404 (corresponding to the control device 200 in FIG. Address data A ₀ to A _o-1 of the call memory 400 is written to the control memory 401 by specifying the address. When writing time slot data A to Z of the input data bus 405 (corresponding to the data bus 301 in FIG. 2) to the communication memory 400, the desired output data bus 4
06 (corresponding to the data bus 302 in FIG. 2), address data A ₀ to _{A o-1} of the call memory 400 corresponding to the time slot numbers t ₀ to t _o-1 are sent to the control device 4.
04 to the control memory 401, and sequentially read out the written address data A ₀ A _o-1 .
The read and written address data A ₀ to A _o-1 are alternately used as write addresses or read addresses of the communication memory 400, and the input data bus 40
5 time slots are switched and sent to the output data bus 406. FIG. 3 shows the time-division call path switch of M1 under random write/sequential read control, but if the read data of the control memory 401 is used alternately as the write address and read address of the call memory 400, the sequential This represents an M1-stage time-division channel switch with serial write/random read control.
This M1-stage time-division channel switch functions as a complete group matrix with no internal congestion, assuming that the multiplicity of the data buses entering and exiting the switch is n, and as shown in FIG. Input terminal 5
00 and n output terminals 501, and the number of intersection points is n×n. Each interface device 201, 21
1, ~, 2n1 and time division channel switch 30
5 uses the data buses 301 and 302 in a time-division manner, so the clock line 303 and the synchronization signal line 304 are
connected with. First, the control devices 200 and 210
A case where data is exchanged using data buses 301 and 302 will be explained. Control device 200 sends data to be sent to control device 210 to shift register 202 . The data in the shift register 202 is controlled by a gate 204 using output signals from a counter 205 and a decoder 206 for generating gate pulses for each time period allocated to the interface device 201, and the data is stored in the time period allocated to the interface device 201. The signal is stored in the memory 306 of the time-division channel switch 305 from the shift register 202 via the data bus 301. Counter 205 is initialized at regular intervals by synchronizing pulses from synchronizing signal line 304, and when counted up by clock pulses from clock line 303, its output signal is developed by decoder 206. By appropriately selecting the output terminal of the decoder 206, the time period in which the data bus 301 is used can be determined for each interface device 201, 211, . . . , 2n1. Memory 30 of time division channel switch 305
The data stored in the data bus 6 is written to the memory 307 from the control device 200 that controls the communication path, and the information on the channel used by the interface device 201 and the channel information used by the interface device 211 are used to control the data bus 302. Device 211
output to the corresponding channel. That is,
The contents of the memory 307 in this embodiment are such that data as shown in FIG. 3 is sent from the control device 200 in FIG. 2 (corresponding to the control device 404 in FIG. 3) to an odd-numbered address in the memory 307. In the case where the memory 306 is in the read state, the random write/sequential read is used as described above, and similarly, when the even numbered address of the memory 307 is specified, the memory 306 is in the write state. This corresponds to the sequential write/random read described above. At this time, the counter 309 and the decoder 308 operate on the memory 306 in synchronization with the data buses 301 and 302.
memory 30 so that writing and reading can be performed.
It operates as a circuit that generates 7 addresses. The data output to the data bus 302 is input to the shift register 213 in a time slot assigned to the interface device 211, passes through the selector 217, and is taken into the control device 210. Since the time division communication path switch 305 is controlled by the control device 200, when data is transferred between other control devices 211, 2n1, the main bus 300 or data buses 301 and 302 are used to connect the control device 200 and the information. By setting the interface device channel information that requires exchange, information can be exchanged between any interface devices using any channel, and the predetermined channel exchange information is written in the memory 307. It is possible even if

As explained above, the present invention uses the auxiliary data transfer path between the interface devices of each control device in a time-sharing manner in a distributed control system.
By using a part of the controlled unit for data exchange, we are able to eliminate the complexity of conventional device wiring, and create a reliable data transfer method that has functions equivalent to or better than conventional devices. This has the effect of being extremely advantageous in terms of implementation and being able to be provided at low cost.

In the above explanation, the time division channel switch, that is, the control device that controls the controlled unit is 1.
However, it is possible to easily realize a plurality of these using conventional techniques, and all of these are modifications of the present invention and are included in the scope of the present invention.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional distributed control system, Fig. 2 is a block diagram of an embodiment of the present invention, and Fig. 3 is a block diagram of a conventional distributed control system.
This figure is a diagram for explaining the operation of the time-division channel switch of this embodiment, and FIG. 4 is a diagram for explaining the time-division channel switch of this embodiment expressed as a space-division switch. 101, 101, ~, 10n...control device, 1
10, 111, ~, 11n... interface device, 120... main bus, 121... data bus, 200, 210, ~, 2n0... control device,
201,211,~,2n1...Interface device, 202,212,~,2n2...Shift register, 203,213,~,2n3...Shift register, 204,214,~,2n4...Gate, 205, 215, ~, 2n5... Counter,
206, 216, ~, 2n6...decoder, 20
7,217,~,2n7...Selector, 208,
218, ~, 2n8... Main bus control section, 20
9,219,~,2n9... bus transceiver,
300... Main bus, 301, 302... Data bus, 303... Clock signal line, 304...
Synchronization signal line, 305...Time division communication path switch,
306...Memory, 307...Memory, 308...
... Decoder, 309 ... Counter, 400 ... Call memory, 401 ... Control memory, 402 ... Address counter, 403 ... Address decoder,
404...control device, 405...input data bus, 406...output data bus, 500...input terminal, 501...output terminal.

Claims (1)

[Scope of Claims] 1. A distributed control system including a plurality of control devices each connected to a corresponding interface device and transferring data via a main bus connecting these interface devices and the interface devices. The data transfer method includes a time division switch controlled by at least one of the control devices, and a data bus connected to all of the interface devices and the time division switch, and the data is transferred between the interface devices. A data transfer method in a distributed control system, characterized in that predefined types of data among data are transferred via the data bus and the time division switch.