SU1515386A2 - Device for demodulating binary signals - Google Patents

Abstract

This invention relates to a radio technique. The purpose of the invention is to increase the reliability of demodulation. The device contains a splitter 1, a multi-branch delay line 2, a unit 3 for estimating the impulse response of the communication channel, adders 4, multipliers 5, shift register 6, geometric addition unit 7, discriminator 8, trigger 9, binary combination generator 10, distributor 11. To achieve the goal, an OR 12 element, a memory block 13, a trigger 14 and an AND 15 element are introduced into the device. The device differs from the prototype in finding the best combination of characters following the analyzed one, as in the sign of the analyzed symbol defined on ceding processing interval, and when the sign opposite to that value. 2 Il.

Description

1515

The invention relates to a radio communication technique, and can be used in discrete information transmission systems via communication channels with dissipation of the energy of received signals in time and frequency and by the improvement of the known device according to the main auth. № 1U78662.

The purpose of the invention is to increase the reliability of demodulation.

FIG. Figure 1 shows the structural scheme of the proposed device; in fig. 2 - plots of narration, which show his work.

The device for demodulating binary signals contains a splitter 1, a multi-drop delay line 2, an evaluation unit for the impulse response of the communication channel, adders A, multipliers 5, a shift register 6, a geometric addition unit 7, a discriminator 8, a trigger 9, a binary generation unit 10 signals, distributor 11, element OR 12, memory blocks 13, additional trip er 14 and element 15.

The device works as follows; at once.

The signal from the output of the communication channel arrives at the input of the splitter 1, the output of which due to synchronous detection with inter-orthogonal heterodyne voltages forms the quadrature components X and Y of the input signal. These components arrive at the input of the multi-drop line 2 delays in the form of voltages that are constant at the clock interval T and are replaced at the boundary between adjacent intervals (Fig. 2a).

Thus, over the processing interval T, from the outputs of the split-line 2 delay, the inputs of the summers 4 are sampled from the components of the input signal. Further, the following notation is introduced:

 the signal component X is counted at the i-M clock interval in the K-th tap of the split-loop line 2 delays (, 2 ... N), the count of the taps is from right to left;

UK, X interference;

. - 1st count of the channel response component (, 2 ... N), the counting is carried out in a natural time sequence;

0 5

0 g 0

five

aj is the sign of the i-th information pitch, the channel response to which is entirely placed in the dividing line 2 of the delay.

In block 3, the estimation of the impulse response of the communication channel is used to estimate the readings in p of this component of the response of the channel. These estimates in the form of slowly varying signals come from the outputs of block 3 to the second inputs of multipliers 5, which in addition to analog (second) inputs contain discrete (first) inputs and can be executed in the form of electronic switches that feed the responses from the outputs block 3 to the inputs of the adders 4 then with a positive then with a negative weight depending on the sign of the control voltage at their first inputs. The multipliers 5 form a matrix, with the row numbers 1 counting upwards, the column numbers counting from right to left, and the diagrams of the first multiplicator inputs. Enter q K-1 (the number of the diagonal), we have for the main diagonal () q 0. With moving to the right up the number of the diagonal decreases to 1-N, and moving to the left down increases to N-1. Depending on whether the first inputs of multipliers 5 are connected to the output of the shift register 6 or the output of block 10, they are divided into first (above the main diagonal, i.e., for qiiO) and second multipliers (qiO). The first multipliers 5 receive control from register 6 shift.

Information symbols, which are the final estimates for the transmitted symbols:

, a;, q -1, -2 (1-n).

The second multipliers 5 receive control from block 10, This is information. the three symbols b;,. „, are trial values (pseudo-estimates) for a

0

14- (|,

s

ftV

a; va, q 0,1, ..., N-1.

Taking into account the negative scaling factor, which can be entered either at the outputs of block 3, or in multiplier 5, or at the inputs of adders 4, at their outputs (the number of adder 4 coincides with the number of tap of the multi-branch line 2 delay

151

matrices are formed

(one)

;, k - 2 ь, „p

eat

-tV i: 4, K

4L g: K-GVe, X

N

Substituted in (1) instead of X; his expression

N x

papuchaem

x.k 2 (a, g-Be ,, - b;, k-e- gj,) +

her i

 Ut. (2)

In the absence of interference (U ;, 0) and with an accurate estimate of the response of the channel sv (SS, K bg.X, there is a combination lb, 4 (j Ga, converting all oL, in O. In block Y of the geometric addition, the squares of all YK P this is the addition of zeros and the input of the discriminator 8 receives the minimum possible zero signal.

In the presence of interference or an inaccurate assessment of the channel response, zero at the output of block 7 is impossible, therefore the task of discriminator 8 is not to register the zero level, but to regulate the minimum of the sum of squares (2) (the sum for all K, X and Y) from the output of block 7. In the general case, this minimum may occur if the equality b is violated; 4.a, a; .a. If the minimum of the signal at the output of block 7 is reached at b; + t 4 a, and q o, i.e. at the final decision stage regarding a, an error occurs while accepting a message. If the inequality b, + Q a; 4t. when the minimum signal at the output of block 7 takes place at q 0 (at the preliminary solution stage), then an error does not occur and equality can be restored at the next (1 + 1) -th clock interval.

The process of processing the received signal on the Interval T in the proposed device can be divided into the following steps.

1. At the boundary between (1-1) -m and i-th clock intervals, the initial conditions are set in block 10, information from the corresponding block 13 of memory q O (number of block 13 of memory equals the number of 38

At q S: 0, the agonal is rewritten into the reg 6 ip register a shift, and the B information is shifted by one bit, and the information content of the remaining N-1 blocks 13 is written into the search 10 cells. At the same time, the contents of the q-ro memory unit 13 is rewritten into the (q-t1) -th cell of the search of unit 10.

Q These operations occur upon receipt of a clock pulse. This search step is a shift.

2. During the i-ro clock interval to the clock inputs of block 10 and

The 5th shift register 6 does not receive any pulses, but 2N pulses are sent to the second block inputs from the outputs of the distributor 11, each odd 0 pulse (Fig. 26, d, e, h) is also fed to the second input of the trigger 9, set it to state 1 (S input). Thus, the trigger 9 during the clock interval N times

5 is set to state 1.

The pulses applied to the second inputs of the unit 10 from the odd outputs of the distributor 11 (counting from top to bottom) are called 11 pulses of the sample, and their pulses fed to the second inputs of the block 10 from the even outputs of the distribution 11, are called return pulses. When another sample pulse arrives, for example, from the first (odd) output of the distributor 11 to the input of block 10 at the (NI) -M output of block 10, associated with the (K-1) th diagonal of the multiplier matrix, the control signal changes to the opposite. This is one of the iteration steps (trial).

If the next sample leads to a decrease (by comparison with the previous samples) of the signal at the output of the block 7 geometrically, then at the output of the discriminator 8 a pulse occurs which takes nocTyisaeT to the first input of the trigger 9 and sets it to the zero state (R input). In this case, from the output of trigger 9 to the input block

five

0

five

When 10 arrives, there is no signal.p that prevents the passage of an even pulse (return pulse) into the looping circuit. Thus, the state of the brute force cells in block 10, resulting in a decrease in the signal at the output of block 7, is preserved. At the same time, the content of the brute force cell 10 (N-dimensional vector of binary symbols, obus

loiivi signal reduction at the output of the 7 addition geometric block 7) from the outputs of the 1U block through the first inputs of the memory blocks 13 is copied to the memory blocks 13 with an impulse maximum, which from the output of the discriminator 8 is fed to the second (memory) inputs of the bp 13 memory ti

3. If the arrival of the next sample pulse (Fig. 26, d, e, h) from the odd output of the distributor 11 to the corresponding second input of the unit 10, the change of the control signal to the opposite (the next test) output on the output corresponding to this input does not result to the reduction of the signal at the output of block 7, the discriminator 8 does not generate a pulse and, therefore, overwriting this variant of the character vector b; + o.1 determined by the current state of the brute force cells of block 10 into memory blocks 13 is not performed. In addition, since the pulse at the output of the discriminator 8 is absent, the trigger 9 remains in state 1, so the next even pulse (return pulse) (Fig. 2c, g, g, i) passes and block 10 and returns it to its original state The situation in which it was installed at the first stage is on the border of the clock intervals (shift). This is also one of the steps of busting - return. Thus, if a sample is an optional check, then a return is a step that can be taken or not. The return is carried out only in the case when the next sample does not lead to a decrease in the signal at the output of the flea 7, as a result, and a targeted selection of simol b, for a fixed (value determined on the previous hex interval), leading to a decrease in the difference in the expected sieve generated in the matrix of multipliers 5 from the received one, i.e., the search for the optimal estimate of the signal generated by the vector of symbols is carried out

   , following the analyzed symbol, provided that the symbol takes the value obtained at the previous (i-l) -M clock interval, i.e. B;, | The optimality criterion is the minimum of the squared difference of the meleda by the received (analyzed) signal and the signal.

0

5 0 5 s

0

five

0

0

formed in the matrix of multipliers 5 based on the evaluation of the channel response, the samples of which come from block 3, and combinations of binary symbols formed in block 10.

If the symbol is a symbol b, o of. The previous processing interval was determined correctly (b; c,., Ui b; + o), the minimum of the square difference between the analyzed signal and formed in the matrix of multipliers corresponds to (bitwise) a, h, q 0.

If, on the (i-l) -M clock interval, o11.1 occurred, the box in the definition of the sign., B; a; Vo ° V above condition may not occur. Indeed, with b,. 1 according to the criterion of optimality, tends to choose a tag of N combination of symbols j L 1, with

condition bj which provides-; The minimum of the square of the difference between the signal being analyzed and the signal generated by the vector of symbols Гь,, q О, and .. In this case, the vector can be chosen (, q O, the value of the body but differs from the actual value of / 0 {a ; +, q О, therefore, with a probability close to one, the last sample in block 10, which inverts the value to the opposite, will not lead to a decrease in the signal at the traveling speed of block 7 and, therefore (according to the prototype), the last impulse to return the cell Terminal block 10 with the number in the initial state.

Thus, as a final, an erroneous decision regarding the sign of the symbol b will be fixed, which at the border between the i-th and (i + 1) -M clock intervals are trans- ported into shift register 6.

In order to eliminate the situation described in the proposed device, the search for the best combination of symbols,, q, q O, is performed as with b ,. Q

 (i-.) + t Р b, Cho,), (opposite in sign obtained on the (i-l) -M processing interval).

The goal is as follows.

The last sample pulse coming from the output of the distributor 11 to the corresponding second input of block 10 changes the sign of the symbol b, Vo is opposite, but unlike the prototype, the return step in the proposed device is not implemented regardless of whether the last sample reduced the signal the output of block 7 or not. In addition, taking into account the possibility of erroneous determination of the character of the symbol on the previous (1-1) -th processing interval and that in this case the best vector of symbols

G 1

l i + ll formed under the condition b:,. quite different in

H t N- "

i t - VHri the last return pulse from the last fourth output of the distributor 11 is fed to the fourth inputs of the block 10 and returns (inverts) the entire vector of symbols G t

1 + 0 t 1 + 0

structure from ia

.one. J formed under the condition bj4 b (;; h,. In addition, the last return pulse goes to the second input of the element 15, the first input of which at this time is supplied by the enable level 1 from the output of the additional trigger 14, which is set to state 1 the first impulse of the sample coming from the first odd output of the distributor 11 to the second (counting) input of the additional trigger 14.

The last pulse of the return from the output of the element 15 through the element OR 12 is fed to the trigger input of the distributor 11. After that, the entire cycle of operation of the distributor 11 and the block 10 of forming combinations of binary symbols is repeated, but as the initial conditions from which the search for the best vector N- one

characters

g.-.

subject to b.

B ({, in this case, uses the vector of symbols, the inverse of the best vector of symbols found under the condition b, Cho b (u ,,.

In this case, the first impulse of the sample (FIG. 2b) of the second cycle sets an additional trigger 14 to the state O, thereby prohibiting the passage of the last return pulse through the element 15 to the trigger input of the distributor 11 and prohibiting its re-launch.

If in the second cycle of operation of the distributor 11 and block 10, the vector of symbols will be found

(,) ::,

more

0

five

0

five

0

five

0

five

0

five

similar in the sense of the optimality criterion to the actually transmitted

H T | a; I, it will be written into memory blocks 13. If such a vector of symbols is not found, then the best vector of symbols of the first search cycle will be stored in memory blocks 13,

In the proposed device, the last return pulses in both cycles :, the operation of the distributor 11 and block 10 act as additional sample pulses in the sense that they form new combinations in block 10

G 1 symbols L V, the expansion of the sa - "V t

Mym search area in the space of received signals and, as a result, increasing the reliability of receiving messages.

The last impulse of the sample in the second cycle of operation of the distributor 11 changes the value of the symbol b, to the initial (b, cho b (i-,) +,), the last return pulse that follows it inverts

 R t best vector of symbols | B (,

the second search cycle, thus making an additional sample, but does not pass to the trigger input of the distributor 11, since the first input of the element 15 has a prohibiting level O, which is removed from the output of the additional trigger 14 set to the state O by the first impulse of the second cycle work distributor 11,

The next cycle of operation of the distributor 11 starts after the next clock pulse (fig.) Arrives at the trigger input of the distributor 11 (see FIG.) Which is fed to the input of the distributor 11 through the first input of the OR 12 element. In addition, the next clock pulse is fed to the first input (R input) of the additional trigger 14, setting it to the state O (FIG. 2l) or confirming this state. The clock pulse also rewrites the contents of memory block 13 with the number as final decisions regarding the sign of the symbol a into the first cell of the shift register 6, and the contents of the remaining memory cells into the search cell of block 10 (as initial conditions in the first

eleven

151

the search cycle in the next interval

processing).

Claims (1)

Invention Formula A device for demodulating binary signals by aut. St. No. 1078662, characterized in that, in order to increase the reliability of the demodulation, memory blocks and an additional trigger, an AND element and an OR element, whose output is connected to the distributor clock input, are entered into it, the corresponding outputs of which are 5386 2 Add to the second input of the AND element and to the first input:; a new trigger, the second input of which is connected to the second input of the OR element and the second input of the shift register, the first input of which is connected to the output of one memory block, the first input of which is connected to the output of the discriminator and with the first inputs of other blocks of memory, the outputs of which are connected to the additional inputs of the block for generating combinations of binary signals, the outputs of which are connected to the second inputs of the blocks of memory. ten