SU1515375A1 - Duplex transceiver of signals - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to improve noise immunity by compensating for echo signals. The device contains an input matching unit 1, a switch 2, two DACs 3, 11, ADC 4, r-5, two memory blocks 6, 10, a sequencer 7, a subtractor 8, an adder 9. To achieve a goal, an adder 12 is entered into the device , four registers 13-15, 18, counter 16, addressing block 17, and AND 19 element. During duplex transmission, three simultaneously occurring processes occur: 1 process - recording the sum of counts of transmitted echo signals and received signals

P process - calculation of the estimate of the echo signal obtained as a result of adaptation to the parameters of the communication channel

Ø process - memorization of the calculated estimates of the echo signal, their compensation in the total confluence and conversion to the analog form of the received signal. Thus, in one frequency band, duplex transmission of signals is organized, compensation of the signals of its transmitter at the receiver input and the output of these signals to the consumer. 2 hp f-ly, 3 ill.

Description

one

(21) kS 4 0/2 -0

(22) 12/15/87

(46) 10/15/89. Bul N ° 38

(71) Novosibirsk Electrotechnical Institute of Communications. N.D.Purtseva

(72) V.B. Malinkin (53) 621.393.3 (088.8)

(56) USSR Author's Certificate M 1133675, cl. H Qi K 1/52, 1983.

(5) DEVICE FOR DUPLEX TRANSMISSION AND RECEIVING SIGNALS

(57) The invention relates to telecommunications. The purpose of the invention is to improve noise immunity by compensating for echo signals. The device contains an input matching unit 1, switch 2, two D / A converters 3, 11, ADC.4, r-5, two memory blocks 6, 10, sequencer 7, subtractor 8,

adder 9. To achieve the goal, an adder 12, four registers 13-15, 18, a counter 1b, an addressing block 17 and an AND 19 element are entered into the device. In duplex transmission, three simultaneously occurring processes occur: I process - recording the sum of counts transmitted by echo -signals and received signals; II process - calculation of the estimate of the echo signal, obtained as a result of adaptation to the parameters of the communication channel; The third process is storing the calculated estimates of the echo signal, compensating them in the total flow, and converting them into analogue form of the received signal. Thus, in one frequency band, duplex transmission of signals is organized, compensation of the signals of its transmitter at the receiver input and the output of these signals to the consumer. 2 hp f-ly, 3 ill.

§

cl

furl

. The invention relates to telecommunications and can be used in data transmission devices over communication channels.

The aim of the invention is to improve noise immunity by compensating for echo signals.

Figure 1 shows the structural and electrical circuit diagram of the device; Fig. 2 is a structural electrical layout of an input matching unit; Fig. 3 is a structural-electric circuit of a sequence generator.

The device contains an input matching unit 1, a switch 2, a first digital-to-analog converter 3, an analog-digital converter, a generator 5, a first memory block 6, a sequencer 7, a reader 8, a first adder 9,. the second memory block 10, the second digital-to-analog converter 11, the second adder 12, the first register 13, the second register l, the third register 15, counts 16, the addressing block 17, the fourth register Ib, and And 19.

Block 17 addressing contains a register 20, the first adder 21, the second adder 22 and the decoder 23.

The input matching unit 1 contains an adder 2 modulo two, a switch 25, a block of permanent memory 26 trigger 27, a counter 28, and a delay line 29.

The shaper 7 sequence contains the counter 30 and the selector 31 zero crossing.

The device works as follows.

The operation of the device can be divided into the adaptation process for the parameters of the communication channel and the duplex information transfer process.

The adaptation process to the parameters of the communication channel is as follows.

Immediately after turning on the device, all the existing blocks are zeroed out and are reset to their initial state. From the terminal equipment, the data on the control output enters the logical unit at the time of adaptation. On this signal, for the period of adaptation, the second memory block 10 is nullified for the communication channel parameters, element 19 and 19, as well as the output of the sequencer 7 of the sequence through a closed switch are opened

ten

20

five

15 -

2 is connected to the input of the input matching unit 1. A short sync pulses are received at the input of the generator 7 of the sequence by the synchronization output from the data terminal equipment.

These sync pulses go to the counting input of counter 30. Thus, if sync pulses are received at the input of the counter 30 with the following frequency f B (where B is the information transfer rate), then the output of the counter 30 will be pulses with the frequency

the following, where m is the division ratio of the counter 30.

The division factor m of the counter 30 is chosen from the condition

(one)

m

..L

 T

five

0

0

five

g 0

where L is the duration of the impulse response of the echo tract;

T is the duration of one information signal. The pulses from the output of the counter 30 are the sensor of information symbols a ;, under which the device is trained (adapted) for the parameters of the communication channel. At the same time, the signal from the output of the counter 30 of the sequencer 7 is fed to the input of the zero crossing 31 selector, in which the boundaries of 5 transitions of information symbols are selected, for example, when going from a to a, from a, 2 to a, etc. These transitions are marked by short pulses.

Thus, the input signal of the input matching unit 1 is fed from the output of shaper 7 of the sequence an information signal a ;, as well as a clock signal, which marks the beginning of each character a;; with short pulses.

In addition, a synchronization signal from the data terminal equipment is transmitted to the third input at a frequency equal to the information transfer rate B. The information signal generated by the sequence generator 7 is m times longer than the real signal a ;, which will be transmitted over the communication channel.

The information symbol a at the first clock interval in the input matching unit 1 is applied to the input of the adder 2 modulo two. Since the first time line of the delay

29 has been reset, then modulo two zero is input to the adder. The adder output signal can be written by the expression

blew yeah

I

And where

(

.

;they

 3;

+ a;

(2)

1-1 ovuch

obum

informational symbols transformed according to the law of relativity on the i-M and (i-1) -M clock interval; information symbol to be transmitted; @ is the modulo two sum operation.

The beginning of each information symbol a; TBCH - ° P - - A - a short sync pulse that arrives at the embedding input of the trigger 27. At the same time, the pulse input of the trigger 27 is supplied with a pulse sequence, and the setup input is a signal from the first output of the data terminal equipment.

The signals supplied to the zeroing and setup inputs of the trigger 27 are prior to any other signals. A logical unit signal is applied to the setup input during the adaptation period, so for this period of time this signal does not participate in trigger control 27. 3, the control of trigger 27 for the adaptation period involves signals arriving at the zero and clock inputs. Since the signal arriving at the zero input has priority over the clock signal arriving at the clock input, then at the first clock interval with the start of the first training a trigger 27 is forced

but set

the

to zero state. The signal from the output of the trigger 27 controls the operation of the switch 25, thereby the output of the adder 2 modulo two. turns out to be connected to the input of memory block 2b. Thus, in the first clock interval of the first training signal, the first information symbol a-, recoded in accordance with expression (1) according to the law of relativity, is fed to the input of the memory block 26. One thing.

20

45

ten

. the temporal sync pulse briefly zeroed the counter 28. At the end of the sync pulse, the counter 28 under the action of the clock pulses from the output of the generator 5 begins to change its state from the minimum value to the maximum value. The code supplied from the output of the counter 28 in conjunction with the first training symbol a, 3F, is the address in the permanent memory unit 26, where the working 15 of the Signal 15 signal is recorded in the corresponding cells. (kut). So, at the address (t obuu 00 .... 00) the countdown Spoij, (kbt) is stored. The subscript of the address code means the number system, the value of k, l t is the discrete instant of time when the first operating signal appears. Binary samples, (k; ut) sequentially appear at the output of block 2b of the permanent memory and are fed to the input of the second digital-to-analogue converter 25, where they are converted into an analog signal Spo5, (t). The signal SpQ6.i (t) is fed to the input of the communication channel and further towards the opposite station. Simultaneously, during the adaptation period, the signal Spai., I (t) is a learning signal for the first signal of the first clock interval.

After the arrival of the second clock pulse, the trigger 27 returns to the one state, since, according to the installation input from the output of the generator 7, there is no sync signal and the trigger 27, under the action of the clock, writes a logical unit supplied to the information input. Under the action of the signal of the logical unit from the output of the trigger 27, the switch 25 connects to the input of the block 26 a constant logical zero.

Therefore, in the second clock interval, the address for the fixed memory unit 26 will vary from (000 ... 00) to (011.L); at the corresponding addresses in the permanent memory unit 26, zeros are stored.

Therefore, after the termination of the action of the first information symbol, a / o & uch, at the first clock interval at the input of the fixed memory unit 26, at the next (t − 1) clock intervals, the zeros arrive at the address inputs. The situation is similar with other information symbols. Indeed, when the counter 30 counts

AP

35

40

50

55

m pulses, then a sync pulse appears at the output of the zero transition 31, which again sets the trigger 27 to the zero state. At the output of modulator 2 modulo two, the second information symbol appears, recoded according to the oTHOi 1 1 law, Counter 28 is reset by the sync pulse to zero and begins to change its state from the minimum to the maximum value. An address is given to the inputs of block 2b of the permanent memory, starting from (000 ... 00) to (agouch ll-lOj) The second line of the fixed memory block 26 is accessed, from which the counts of the second working signal Spae-iCkut are output) . The second, working signal S „g) is again output to the second digital-to-analog converter 11. Thus, during adaptation to the parameters of the communication channel, samples of the working signal Erdc appear from the output of the input matching unit 1. (kut) for the duration of one clock interval. After the end of this clock interval, the input matching unit 1 outputs to the input of the second D / A converter 11 zeros. Such an initial adaptation algorithm is necessary in order to be able to record an echo signal whose duration is much longer than the duration of the working signal. In the process of duplex information transfer, the input matching unit 1 performs the functions of a conventional modulator (amplitude, phase, or frequency).

By looking at how the device is configured for echo signals.

When the first working signal is received — samples from the output of the input matching unit 1, they are transformed by a second digital-to-analog converter 11 to the analog voltage Spog (r), which is fed to the input of the communication channel and further to the opposite station.

The signal Spo, 6, (t), depending on the parameters of the connected communication channel and its state, is converted (collapsed) with the impulse response of the communication channel. Therefore, at the input of the analog-digital converter

five

0

five

0

five

0

five

0

The body observes a sum signal which is equal to:

Xi (t) Spo ,, (t) A g (t) +, (t), (3) where g (t) is the impulse response of the communication link echo path;

; (t) —Shopper coming from the communication channel;

The symbol means a convolution operation;

The signal X (t) B of the analog-to-digital converter A is converted into samples of the digital signal X, (kur), which are fed to the input of the second adder 12.

Since the signal from the control output of the data terminal equipment element And 19 is open, the output of the latter is a pulse sequence from the output of the generator 5, which controls the mode of operation of the first memory block 6. So, if any number is set up at the input of the first memory block 6, the previous contents of this memory cell are first read at this address, and then a new value is written from the output of the second adder 12. The read value from the first memory block 6 is rewritten into the fourth register 18; Simultaneously with the beginning of the formation of the first signal. Ckit), in the input matching unit 1, the first clock pulse resets the counter 1b. After the end of the first clock pulse, the counter 1b under the action of the clock pulses from the output of the generator 5 begins to change its state from the minimum to the maximum value. Relapsed according to the law of relativity, the first informational signal of the output of the input matching unit 1 in combination with the code supplied from the output of counter 1b is the address for the first memory block 6. Thus, during the formation by the shaper 7 of the sequence of the first training information symbol a, in the first memory block 6 the addresses change, starting with. (a, .. .00) 2 and ending with (,,,).

Since the first memory block 6 was initially cleared, then the last from the first cell (address ... .., 00) is first read zero, which is then rewritten into a metro-invert register 18. At the output of the second

An adder 12 appears the first count of the total process.

S, xo, (k, bt) Spo, e (k, ut) .- g (k, & t) + +, (k, bt), (A)

which is recorded in the first memory block 6 at (. .oo). Similarly, the countdown case with other counts. So at the address (a | og 00 .. .01, the count S3xo, (kiit) SpoB, (k, & t) g (k & t) + +, () (5)

and so on.

The situation is similar when the input matching unit 1 is formed at the next m clock intervals SpQ6 (k & t) corresponding to the second information symbol ZigQs. the first block of 6 memory at (ajoguq 00 ... OO). a count is written equal to:

S3xoa (k ,, & t) Spo, 6, (k, it) g (kut) + + G. (.it), (6)

where kjbt is a discrete point in time

The memory cell at the address () O0 ... 0l), j is written to the value S., no (k ,, it) SoaB (k, ut) g (kut) +

(7)

 9XOiVi mtT.it) - 5rav (

 ri (k ,, t).

when the shaper 7 forms a two-position signal after the information symbol, agoBitsv is formed again in the first memory block 6, the first memory line in which the counts of the total process S, o, () are stored. With this again

the first time a read is made- 5 removes the positive potential, the

the first memory location S5) (o, (k, ut) from the first memory block 6, which is rewritten into the fourth register l8. In the second adder 12, 85x0 is added, (k, bt) and S-, xo, () The result of the addition will be: S9xo, (ku ,, ut) S3xo, (k, bt) +

+ S, xo, (k2n, .. ut)

(eight)

Sgxo, (k, & t) and S ,, o, (k2,, ut) are samples of the transmitted signal at different points in time.

Thus, after transmitting the training signal N times, the value of m will be stored in the first memory block 6.

Zakho,) ± Sp ,, (k.) GCkut) + I m (-1

+ & ftut). (9)

.one. . Multiple training is necessary

in order to average the effect of interference in the communication channel, and thereby improve the quality characteristics of the device as a whole,

the forced zero signal from the second memory block 10 is removed as well as the switch 2 shuts off the output of the sequence maker 7 from the input of the input matching unit 1. In addition, the element 19 is closed, thereby the first memory block 6 goes into count mode - information, therefore, the echo signals received during the training process remain unchanged during the communication session.

The input of the input matching unit 1 is connected after training to the information output of the data terminal equipment. Since the sync pulse no longer 55 enters the input matching unit 1 from the output of the sequencer 7, and a logical zero arrives at the setup input of the trigger 27 from the output of the data terminal equipment after completing the training, the last

50

ten

15

1537510

As can be seen from the formula (9), in order to have an estimate of the echo signal,

20

25

thirty

S9xo, (kAc) divided by N. Division by N is made in the fourth register 18. In order to divide the obtained count by N, the value of the Zэcho count is necessary. (ku.t) shift by Z bits in the higher bits so that 2 N, where Z is the number of dump bits. For example, if N is chosen equal to 6, then we discard 6 least significant bits and thus divide by b. Thus, after the device has been adapted to the parameters of the communication channel, the input coaxial Oloc 1 generates N times the working signals of Spa6, (t) and), and the N-channel will respond to these working signals by the echo signal N times. The readings of this echo in the form of a binary number are recorded in the first memory block 6. When training a device for the parameters of a communication channel, the read speed and recording of samples from the first memory block 6 is equal to the speed of generation of working signals. This mode is provided by supplying the clock frequency to the input of counter 1b exactly the same as that to the input of counter 28 in the input unit 1.

After iterating through the N information symbols a, og i oKOHe4Hoe equipment data on the control output

removes positive potential

the forced zero signal is removed from the second memory block 10, and the switch 2 also disconnects the output of the sequence maker 7 from the input of the matching block 1. In addition, the AND 19 element is closed, thereby the first memory block 6 goes into read only mode information, so the echoes received during the training process remain unchanged throughout the communication session.

The input of the input matching unit 1 is connected after training to the information output of the data terminal equipment. Since the sync pulse from the output of the sequencer 7 no longer enters the input matching unit 1, and from the output of the data terminal equipment after completing the training a logical zero arrives at the setup input of the trigger 27, the last

is set to the termination state of the communication session and connects the output of the adder 2 modulo 2 2 to the input of the fixed memory unit 26.

The input matching unit 1 is thereby converted by properties into a conventional amplitude, phase, or frequency modulator. The type of selected modulator is negotiated before the session by the corresponding entries in block 2b of the permanent memory of the operating signal counters, which correspond to the types of modulation listed above.

How is the duplex information transfer performed? When duplex transmission occurs. three simultaneously proceeding processes. The first process is recording the sum of samples of transmitted echoes and received signals. This operation is performed using an analog-to-digital converter 4 and a second register lA.

The second process is the process of calculating the estimate of the echo signal obtained as a result of adaptation to the parameters of the communication channel. This process is performed using the first 6 and second 10 memory blocks; first 13 third 15 fourth 18 registers; the first 9 adder, counter 1b, addressing block 17, consisting of the first 21. and second adders; register 20 and decoder 23.

The third process is storing the calculated estimates of the echo signal, compensating them in the total flow, and converting them into analogue form of the received signal. This process is carried out with the help of the third register 15, the subtractor 8 and the first digital-to-analog converter 3. Let us consider in more detail the implementation of the first process - the process of recording the signal coming from the communication channel.

The received signal y, (t) comes to be separated from the transmitted signal (in our case, this is Spae .; (kut)). Let the first information symbol a, be received at the input of the matching block 1. According to expression (1), this information symbol a is recoded modulo 2k in the adder 2k and delay lines 29 into relative information

0

five

0

five

0

five

0

, (k & t)

signal a. The value of this information symbol a, together with the counter code 28, indicates the memory area of the fixed memory unit 26, in which the samples of the first operating signal are stored). These samples, passed the first digital-to-analog converter 3, / are converted into analog signals S gg ( t), which are then fed to the opposite station. Simultaneously with the formation of the working signal SpaQ, (k & t) in the input matching unit 1, the second output of the last appears a relative information symbol a, which, together with the counter code 1b, indicates in the first memory block 6 a memory region in which the response is written communication channel to the first working signal.

As mentioned above, the number of samples required to form the working signal n is less than the number of samples of the recorded echo signal d when working on real communication channels 1 due to the presence of reactive elements, as well as the presence of differential systems of voice frequency channels. Therefore, the processing speed of the echo samples should be at least d / n times higher than the speed of the working signal. At the input of the analog-digital converter k, we observe the sum of two signals: the echo signal and the received signal, and at the output of the analog-digital converter 4, the same sum, but as a binary number.

X, (k, ut) S3xo, (k, ut) + Y, (k, ut) (10) Here k, t denotes the first discrete instant in time when we observe the sum of two signals at the output of the analog-digital converter k at duplex exchange. This counting X, (k, ut) from the output of the analog-to-digital converter k, then goes to the second register And, having a length equal to n consecutive slots k bit words. Therefore, at the first moment in time, the count X, (k, & t), is written into the first column of the second register I. At the next time point at the output of the analog-digital converter k, we observe a signal X (), equal to: X,) S, xo, () + Y, (kjut). (eleven)

After the appearance of the reference X, () the latter is written to the first table13

Beat the second register, and the previous content of the first column, i.e. X () is rewritten in the second

column and so on. After the last reference of the working signal is formed by the input matching unit 1, the second register 1 is completely filled. When forming the first one, the second operating signal in the first column of the second register, k, will record the total process time, consisting of the main part of the second working signal, the received signal at the second clock interval, and the echo signal from the first working signal, i.e.

X (k „,, t) S ,, o (k, & t) + Y (k, At) -n + S5xo, (kn., T:) (12)

These samples in the second clock interval are also sequentially downloaded to the second register-14 ,. advance the previous recorded countdown to the input of the subtractor 8.

The situation is similar with other counts.

According to a snapshot in more detail, the essence of the process occurring at the moment is the process of forming an estimate of the echo signal. From the analysis of formulas (10) - (12), it is clear that to each received sample g, (kfi, echo signals are added, which need to be worked out and further compromised as mentioned above. When forming the first working signal at the first clock interval the relative information symbol aj appears in block 1 at the output of the latter. The value of this symbol in combination with the code supplied from the output of counter 16 indicates in the first memory block 6 a memory area in which the echo sample S is written, o (kut). Counts 1b to It begins to change its state, thus the first echo counts appear at the output of the first memory block 6. As mentioned above, the first echo counts with repeated training turned out to be N times the actual echoes. the readings of the first echo, the fourth register 18, in which from

r minor bits are thrown; the memory block 10 is written to the values ./JJ, h (-p-1

are divided by N (if 2 N is satisfied).

Thus, when the address changes at the first clock interval

echo, (. ,, it), single m signal s ()

on), at B,

S ,. (kj. it), and at

first echo- while the first

magnitude

 - last countdown

I /

from (a; 00 ... 00) ,, А ° „to Af (aj 11 ... 11) g at the output of the fourth register

18

counts of the first echo (kit) appear sequentially. These samples are then fed to the first input of the first adder 9, which, together with the second memory block 10, the first register 13, the addressing block 17, and the third register 15 generates an estimate of the echo signal at the first clock interval. According to how this is done, in more detail. Let the first

the time point (first clock interval) the addressing unit 17 generates an address for the second memory block 10 synchronously with the addressing for the first memory block 6. Thus, if the address A ° o (a, 00 ... 00) is indicated for the first memory block 6, for the second memory block 10 the ad20 is indicated

five

0 5

0

five

0

res (00 ... 00). Similarly with other addresses, if for. The first

I then

memory block 6 indicates address A (a, 00 ... O), then address B is indicated for the second memory block 10.

Yu

 (00 ... 01) 2, etc. Hereinafter, subscripts (i.e., 2 and 10) denote the numeration system. The order of generating such an address will be explained below.

Since the second memory block 10 was forcibly reset at the time of training for echoes (kut)

by a signal from the output of the data terminal equipment, in the second memory block 10 all zeros are stored at all addresses at a given time. The order of access to the memory cells of the second memory block 10 is as follows. At the beginning, the previous content is read from a cell at a given address, and then the result of summing up from the output of the first adder is recorded at the same address. Thus, from the cell with the address B of the second memory block 10, first at the first moment a zero is read, and then the result of the summation from the output of the first adder 9 is recorded, i.e. the quantity S ,, o, (k.t) + О S5, o, (k, t).

Similarly to address B, in the second

  .. h (-n-1

echo, (. ,, it), single m signal s ()

on), at B,

S ,. (kj. it), and at

first echo- while the first

magnitude

 - last countdown

The n counts of the first echo are simultaneously stored in the third register 15. This will be the estimate of the total echo signal at the first clock interval. With the beginning of the second clock interval, the addressing unit 17 begins addressing for the second memory block 10 with a shift by the value of n. So

but

Thus, if for the first block 6 the first address accumulator 9 will only generate address A, (a, 00. ,, 00) 2, then for the second memory block 10, an address equal to

A ° o + y When the counter moves 1b to the next- -js itself

The state of the first block 6 of the memory of the second echo signal S xo Ckj-n or): S, o (l d-nvibt); ... S9xo (kjut).

These readings are recorded at an address. E; „, ,,, respectively 10

proper

These are the address equal to A ,, (a 00 ,,, 01)

one

and on the second block 10 memory

At the third clock interval / 17, the addressing again moves its addressing by another n. Thus

TI produces an address equal to B

4VJ

Thus, from the beginning of the second, 20 if the output of the counter is 16 addresses

  At the same time interval, the reading and writing in the second memory block 10 is made with a shift by n relative to the first clock interval. If at the output of counter 16, together with the recoded character, addresses in A, A | o, A fp., .. appear on the second clock interval. ,

OK

BUT

ten

10 A, THAT at the output of the block 17

vary as n.g, p, d, "w

The procedure for accessing the BTOPOM memory block 10 will be as follows: In

25 V

7rt + 1 (o

AT

, 7g. t 2 „d

, L. °

ten

AT

You are “-1”

1.1 g, g

D lt D

10 10

, Corresponds

 U 10 10

The output of the first adder will be the echo signal counts.

,,,BUT

addresses appear for the second

, d, then at the output of block 17, the form is 30 .dMUt) + 5 "og (. U t) +

memory block 10 respectively in video

() -

0 - CHO

(/ h

AT

+ n, o) B

ip

io 5., 10, „(

- B, g,; AT ," ; AT,. ; AT,

p-1

R

(O (O 10 0

  - o Then, with the start of the second clock interval, from the first block 6 of memory at address A is read (k, it), and from the second block 10 pm of data at address |,

- S value

9iro,

(kj, At); Similarly, the address A is read from the first memory block 6),) from the second memory block 10 is a count; S ,, yo, () and t, d. is the sum of two samples (at the first moment) S, xoj (k, t) +,). In the next moment, this amount will be equal to) + S, xo, () and t, d. The result of the summation of the first adder 9 is recorded again in the second memory block 10. So by the address is written the amount equal to

and on S5xo., () + S, o, (4, f, t

(k,) -t- S, o, (k, b t), pecy B ;; -) +

The state of the estimator l6 is decrypted by the decoder 23. Moreover, if the counter 1b changes its state from A ° Q to, then at the output of the decoder 23 there is a logical one. EC

If the state of the decoder 23 changes from to, then the output of the decoder 23 is a logical zero. This signal from the output of the decoder 23 forcibly zeroes the first register 13. Thus, at the input clock interval when the state of the counter 1b changes from A, to A. At the output

but

the first adder 9 will be only otsam

scores of the second echo signal S xo Ckj-n e): S, o (l d-nvibt); ... S9xo (kjut).

These readings are recorded at an address. E; „, ,,, respectively 10

proper

In the third clock interval, the block / 17 addressing again moves its addressing by another n. Thus,

  A a

ten

10 A, THAT, at the output of block 17, is adigreetized as n.g, p, d, "i

The procedure for accessing the BTOpOMi / memory unit 10 will be as follows: In

2ts

5 V

7rt + 1 (o

AT

, 7g. t 2 „d

, L. °

ten

AT

You are “-1”

1.1 g, g

D lt D

10 10

, Corresponding Yu 10 10

The output of the first adder 9 will be the flags of the echo readings

in the form of 30 .dMUt) + 5 "og (. U t) +

 + S5); ((t)

S ,,

S ,, o, (4ut) + S5xoi ()

. (k

EUW

ut);

(kj .. & t)

, (kd-7., ut) +, ();

40

):

S.xo, (

, (kd-n4, ut) 5 S.xo, (kj-nvi t);

0

five

5eho, (kjut).

The first n samples of the total process from the output of the first adder 9 are again zag (they are sent to the third register 15, which characterizes the estimate of the echo signal at the third clock interval. The process proceeds in a similar way at other clock intervals.

By taking pictures, how are the processes in block 17 addressing. As shown above, in the first clock interval at the output of the addressing unit 17, the order of accessing the memory cells will be the same as that of the first memory unit 6. However, the efficiency of generating an estimate of the echo signal does not depend on the state from which the first memory starts to the memory cells of the second memory block 10. Let the number p, o be stored in the register 20 at the first time instant. Then the output of the first adder 21 will be a value equal to-п, о + п, о 0. Thus, the second input of the second adder 22 is given a logical zero, therefore the output of the counter 16 is freely passed to the output of the second adder 22, thereby ensuring synchronous addressing for the first 6 and second 10 memory blocks.

From the beginning of the second clock interval, its beginning is accompanied by a clock pulse from the data terminal equipment, thus the state of the first adder 21 is written to the register 20. As shown above at the output of the first adder 21, there was a logical zero. Then, at the output of the first adder 21, a signal equal to n, o appears, which is fed to the second input of the second adder 22. Thus, the address is increased at the second clock interval for the second memory block 10 at the p.

Similar processes on the third clock interval. Indeed, after writing to register 20 with the start of the third clock signal interval n, (, the output of the adder 21 at the output of the latter appears to be about 10 2p (oh and so on.

According to the third process, the process of compensating the readings of the echoes in the summary process coming from the communication channel. As shown above, the total process coming from the communication channel is stored in the second register 1, and the echo estimates are stored in the third register 13. After the end of the echo estimation is completed, the latter are sequentially received from the second output of the analog-to-digital converter ( the strobe-pulses of the end of the conversion) begin to be read from the third register 15. At the output of the subtractor 8, only the received signal arrives from the opposite station from the channel

connection, which is then converted by the first analog-to-digital converter 3 to an analog value and provided to the consumer.

Thus, in one frequency band, duplex transmission of signals is organized, compensating for signals of its own. transmitter at the receiver input and output of these signals to the consumer.

Claims (2)

1. A duplex signal transmission and reception device comprising an input matching unit, a switch, a subtractor, a generator, a sequencer, a first memory block, a first digital-to-analog converter, a second digital-to-analog converter and an analog-to-digital converter connected in series, and a first accumulator the second memory block, 5 with the first output of the sequence generator connected to the first input of the switch, the second input of which is connected to the second input of the second memory unit, the generator output is connected to the first inputs of the input matching unit, the analog-digital converter, the first memory unit and the third input of the second memory unit, with the aim of improving noise immunity by compensating for echoes, the first, second and third registers are entered, the AND element, serially connected counter and addressing unit, the fourth register connected in series, and the second adder, the output of which is connected to the second. The first, first, third, fourth, and fifth inputs of the memory block are connected respectively to the outputs of the counter, element I, and the first output of the input matching block, the output of the first memory block is connected to the first input of the fourth register, the second output of which is connected to the first input of the first an adder, the second input of which is connected to the output of the first register, the first and second inputs of which are connected respectively to the output of the second memory block and the perch output of the addressing unit, the second output of which is connected to the fourth to the input of the second memory unit, the first output of the analog-digital converter nineteen connected to the first input of the second register and the second input of the second adder, the second output of the analog-digital converter is connected to the second input of the second register and the first input of the third register, the second input and output of which are connected respectively to the output of the first adder and the first input of the subtractor, the second input and output which is connected respectively to the output of the second register and the input of the first digital-to-analog converter, the generator output is connected to the first inputs of the counter and the And element, the second inputs of the block a and the fourth register and the third inputs of the first and third registers, the second input of the oracle switch is connected to the second inputs of the input matching unit and the And element, the second input of the counter is connected to the third inputs of the input matching unit and the addressing unit and the input of the sequencer, the second output of which is connected to the fourth input of the switch, the first and second outputs of which are connected to the fourth and fifth inputs of the input matching unit, the second output of which is connected to the input of the second digital-analogue The converter, the addressing block contains the decoder and serially connected register, the first adder and the second adder, the first and second inputs of which are connected respectively to the input of the decoder and the first input of the register, the second and third inputs of which are 5 DA 537520 the eye and the third inputs of the addressing unit, the first and fourth inputs, the first and second outputs of which are, respectively, the input of the decoder and the second input of the first adder, the outputs of the decoder and the second adder. 0 five 5 ZO 0 five 2. A device according to claim 1, characterized in that the sequence generator comprises a series-connected counter and zero-crossing selector, the input and output of which are the first and second outputs of the sequence generator, whose input is the input of the counter. 3 The device according to claim 1, which includes: the input matching unit contains a trigger, a counter, a serially connected delay line, a modulo two, a switch and a fixed memory unit, the second input of which is connected to the output of the counter, the first input of which is connected to the first input of the trigger, the output of which is connected to the second turn of the switch, the output of modulo-two sum is connected to the input of the delay line and is the first output of the input matching unit, the second output, first, second, third, fourth and n in the the course of which is yu yu, respectively, the output of the memory block, the second input of the trigger, the second input of the counter, the second input of the modulo two adder and the third input of the trigger. (ree.2 FIG.