SU1508225A1 - User to communication channel interface - Google Patents

Abstract

The invention relates to interference-free exchange of alphanumeric information in basic and terminal ACS networks over telephone channels and physical lines in duplex mode. The aim of the invention is to increase the testability and decrease the localization time of the fault. The invention allows to significantly expand the functionality of the device in terms of ensuring the independence of the processes of simultaneous simultaneous testing of data terminal equipment sets in a stream with a useful schedule due to the introduction of data broadcasting units with foreign addresses and transit buffer memory with mechanisms into each of the equipment sets of the data channel equipment. initiating the reading of the contents of this memory at the release of the outgoing communication channel. In each of the stations of the device operating in duplex mode over a channel with a four-wire termination, there are sets of data terminal equipment and data channel equipment, each of which has controlled operative memory with modules of the primary, secondary station implementation of the linear control protocol and transit unit a buffer memory, a broadcast unit, a program and data storage unit, and communication units, respectively, with a subscriber (a set of data terminal equipment) and a modem. 11 il.

Description

independent testing packages; in FIG. 8, the packet format is Call Received; The connection is established to establish a packet of independent test transmission; FIG. 9 shows the packet format. The data of the DTE. The data in FIG. 10 is the packet format. Request to terminate the connection; in fig. 11 — packet format Confirmation of completion.

The device contains a communication channel 1 with a four-wire termination, two identical data stations 2 and 3 subscribers, each of which contains a set of 4 data terminal equipment and a set of 5 data channel equipment. Included data hardware

15 In the control block the control unit 50 implements the measures, on the integrated circuit. On the input links 22-25, the signals are received

16-21 to block I, the address signals, the reception decision gates and the signals ,. memory, resolution

25 Nor, in addition, the block 11 y is connected to the highway 15; the indicated links can be in c. according to interf

thirty

35

there are a block 6 of communication with the subscriber, a memory of 7 programs and data, an operational 20 interrupts, a reset, a seizure of memory 8 with program modules 9 and 10, respectively, of the primary and secondary stations of the implementation of a linear control protocol, a control block 11, a module a torus 12, a demodulator 13, and a communication unit 14 with a modem.

. The operational memory 8, blocks 6 and 14, and control unit 11 are interconnected by links 15-25. Blocks 6 and 14 are connected to the subscriber and modem by links 26 and 27. In the operational memory 8, a transit buffer memory module 28 is entered, the inputs and outputs of which are combined with the corresponding inputs and outputs of the RAM. A translation unit 29 is included in the data channel equipment set.

Translation block 29 contains three buffer registers 30-32, four decoders 33-36, four flip-flops 37-40, four AND 41-44 elements, four encoders 45-48, and OR element 49.

The control unit 11 consists of a microprocessor element 50, a clock generator 51, a control signal generating element 52, an electrical parameter matching element 53, and an internal bus signal clock element 54,

Random access memory 55, a regeneration element 56, a control element 57, an address multiplexer 58, a buffer register 59 and an AND 60 element form the operative memory.

The subscriber communication unit 6 contains bidirectional main drivers 61-63, a command decoder 64, an address decoder 65, an interface

40

45

50

55

The capture signal transmits the data lines to the third impedance, performs forward memory and multiprocessing.

Element 50 provides bytes to the internal trunk bytes of the type of cycle being performed and cycled to element 53 and used to generate signals. In the second cycle of operation, the Gating signal of the Ready signal is processed, the input of the wat is analyzed and the read or write is completed. At the same time, 50 sets trunk 16 and data 15 to a high impulse state and goes to Capture, Last cycle n of the machine cycle - analysis from the input signal. Request n In case of presence of a high signal and compliance with the condition of the interrupt resolution 50, the state is acknowledged on the trunk. n also forms the permission signal.

Matching element 53 of master formers

8225

block 66, reception signal generation element 67; output element 68, response element 69, state encoder 70, operation mode triggers 71-73, AND element 74.

The communication unit with the modem consists of a universal synchronous asynchronous transceiver 75, a decoder

10 76 addresses, a data bus matching node 77, timers 78, an interrogation request message element 79, and a reconciliation element 80 with a C2 interface.

15 In the control unit P, the microprocessor element 50 is implemented, for example, on the integrated circuit K580IK80. Signals are received via the input links 22-25 to the control unit 11: request

On output links 16-21, signals of address, gating, reception and reception signals are transmitted to block II. memory addresses, resolution resolution, In addition, control unit 11 is connected to data line 15. All specified communications can be implemented in. according to the interface AND 41.

20 interrupts, reset, capture

The capture signal via line 25 allows the data lines and addresses to be transferred to the third high-impedance state, direct memory access and multiprocessor operations.

Element 50 provides a status byte to the internal highway, defining the type of cycle to be executed, written to element 53 and used to generate control signals. At the second cycle of operation of the element 50, the input signal Gating is gated, in the presence of which the input signal Grip is analyzed and the read or write operation is completed. Element 50 then sets the address and data lines 15 to a high-impedance state and enters the Capture, Last Clock of the last machine cycle state of the input signal. Interrupt Request In the event of a high level of this signal and the internal conditions for resolving the interrupt are resolved, element 50 There is an Interrupt Acknowledgment status on the data highway 15 and generates a Enable Interrupt signal.

The reconciliation element 53 consists of address formers

and bidirectional data line drivers. The address driver is an eight-bit register that has output circuits with three states. The third high-impedance state occurs when the output level is high. Capture acknowledgment. With a low level of this signal, address line drivers will repeat the signal levels of the element 50 address lines. Bidirectional data drivers support the outputs in the third high-impedance state with a high output signal level of the element 50 Acceptance Capture and the presence of the Accept or Receive signal.

The element of forming signals of the upsoprenna line of the input-output highway 26 of the set 4 of data terminal equipment and the internal bus of block 11. Trunk drivers

61-63 implemented, for example, on schemes K589AP26.

The decoder 64 commands can be implemented on the scheme KI55PE3.

The address decoder 65 is made similar to the command decoder. It provides a comparison of the transmitted physical address with its value in control block 11. In case of coincidence

the corresponding mode trigger is triggered and provides the functional connection of the control unit 11 to the input / output highway 26.

The interface unit 66 performs

52 generates Receive signals, 20 bytes of the transmitted bytes and

Delivery, Acceptance Acceptance, Gating, and Memory Selection Signal Address. Memory address.

The input clock element 54 converts them from asynchronous to synchronous.

Memory 7 is used to store monitor programs. This, for example, is a programmed K565RT5 chip.

 Random access memory 8 is used to store the work program and data sets. In this block (FIG. 4), for example, storage elements on integrated circuits K565RUZA are used. .

The buffer register 59 provides the power interface of the output memory 55 to the data line 15.

The regeneration element 56 is intended for the regeneration of the storage device 55, forms the addresses of the rows which change occurs cyclically, at the end of the regeneration cycle of the next row, implemented, for example, in schemes K155TM2, K155IE2, K155IE5.

The control element 57 can be implemented on the K155TM2, K155LI1, K531LI5, K155LAZ circuits.

The address multiplexer 58 sets the row address and the column address of the cell of the storage device 55 to be accessed, or the address; regenerated line device 55, the interface unit with the subscriber provides energy and logical

received information and storing bytes of the updated state of control block II, is implemented, for example, on the K580IK55 scheme. Block 66 is programmed by writing a control word from element 50 (FIG. 3). The control word register of block 66 defines the function and direction of operation of each of the I / O channels.

Elements 67-69 are implemented respectively on the OR-NOT schemes and the trigger; OR NOT and two triggers; And NOT; And-NOT and inverter.

The state encoder 70 is made on an EPROM, which can be, for example, the circuit K556RT4. The encoder 70 is used for the energy interface of the block 11 with the state highway of the set 4 of data terminal equipment.

The transceiver 75 can be implemented on the chip K580IK51.

The decoder 76 generates signals to access the registers of node 77 in accordance with the address set on the address line. It can be implemented, for example, on the two-input And elements and the K155LAZ, K155VD4 integrated circuits.

Node 77 is designed for power interface with the internal bus and can be implemented, for example, on a K589AP16 chip and the elements OR, I.

Timer 78 is a combination of four single-shotrs that generate clock pulses of a different period to provide a timeout.

7150

Element 80 is designed to match the electrical characteristics of the TTL signals with the parameters of the C2 junction and can be implemented, for example, on the K170AP2 chip.

Modules 9 and 10, respectively, of the primary and secondary stations of the implementation of the linear control protocol are software modules for the implementation of, for example, the ND1S protocol stored in separate memory areas,

As modems 12 and 13, any modem with C2 interface that can operate in two-duplex mode can be used, for example, EU mode 8010,

The module of the transit buffer memory 28 is implemented as one of the areas of the RAM block 8, based on, for example, microcircuits.

Buffer registers 30-32 are parallel eight-bit registers with bidirectional data generators at data station 3 (FIG. 1). The flag byte comes from incoming channel 1 to demodulator 13, at its output in transceiver 75 (FIG. 6). converted from sequential; forms in parallel, the B state register of the transceiver 75 fixes the fact of decoding the flag and the element 79 in the control unit 11 forms

K589AI126 is similar to the buffer register, 59 (figure 4). The work cycle of the buffer registers 30 and 31 contains two sub-cycles. In the first of these, a byte of data is written into the buffer register. The 30 signal is a request to interrupt microprocessor element 50 (FIG. 3). It, in turn, generates an Interrupt Enable signal in block 14. This pr-process is repeated at reception and de 35

on the second, the contents of the buffer register are compared with the standards stored in the memory of the decoders 33-36, implemented, for example, on K155REZ microcircuits.

Encryption elements 45-48 are also implemented on an EPROM, in the quality of which, for example, a K155REZ chip is used.

The device works as follows 40 times.

The initiator of testing is, for example, the operator-terminal equipment of the data Operator computer) station 2 (figure 1). By entering the appropriate 45 command, the operator initiates the transmission via block 6 of the Request Call packet (FIG. 7). In this case, the control unit P allocates a logical channel with a group

encrypt every next flag.

If, after the next flag, a data byte is received (byte of the frame address with the Call Request packet),. this interrupt byte is read by element 50 from node 77 and enters data line 15. Element 50, in accordance with the work program recorded in the RAM 8, addresses this byte from the output of node 77 (FIG. 6) to the input of the buffer register 30 (FIG. 2). In buffer register 31, the status word of module 9 of the primary station is permanently reflected.

On a signal from control unit 11, the contents of the buffer registers 30 and 31 are compared with the standards, stored in 1mis in the decoders 33-35, as a result one of the triggers 37 and 38 is triggered, and the trigger 39 is moved to the position corresponding to ( passive, asset) module of the primary station.9. As a result, through elements 41-44 it is selected and read into buffer register 32 with a total meter (GNLC) less than or equal to 15, and a logical channel number (NLC), which is 255 or less, equal to 255, the logical channel goes to state OOD is waiting.

In the field Services

A single value, for example, the least significant bit, identifies an optional tying service,

Package Request Call

Independent Tes- Block 11, analyzed

five

0

five

This bit sets the Call Request as the address of the DTE — recipient — address of the DTE — the initiator of the test, i.e. OOD address 4 stations 2 ..

In the address area of frame 8, block 11 sets the address of station 2, i.e. Alien for station 3 address.

In standby mode, data from the block. 4 modules of primary stations 2 and 3, independently of each other, transmit flags.

A byte flag from station 2 along chains 15–20 is fed to the input of a 14-in block. parallel form. In block 14, the transceiver 75 (FIG. 6) converts the data into a sequential form and transmits via element 80 to the C2 interface circuit with the modem.

At data station 3 (FIG. 1), the flag byte comes from input channel 1 to demodulator 13, at its output in transceiver 75 (FIG. 6), it is converted from serial; forms in parallel, the B state register of the transceiver 75 fixes the fact of decoding the flag and the element 79 in the control unit 11 forms

0 signal Request interrupt microprocessor element 50 (FIG. 3). It, in turn, generates an Interrupt Enable signal in block 14. This pr-process is repeated when receiving and dec.

0

five

0

five

encrypt every next flag.

If, after the next flag, a data byte is received (byte of the frame address with the Call Request packet),. this interrupt byte is read by element 50 from node 77 and enters data line 15. Element 50, in accordance with the work program recorded in the RAM 8, addresses this byte from the output of node 77 (FIG. 6) to the input of the buffer register 30 (FIG. 2). In buffer register 31, the status word of module 9 of the primary station is permanently reflected.

On a signal from control unit 11, the contents of the buffer registers 30 and 31 are compared with the standards, stored in 1mis in the decoders 33-35, as a result one of the triggers 37 and 38 is triggered, and the trigger 39 is moved to the position corresponding to ( passive, asset) module of the primary station.9. As a result, through the elements AND 41-44, the contents of one of the encoders of the address pointers are selected and read into the buffer register 32, by which further translation of the given and all other bytes of the received frame is possible. Then block 11 reads the contents of the buffer register 32 into the specified area of the operating memory (translation domain) and to the address line and reads the contents of the buffer at the given station in the broadcast register register at this address.30. As the next bytes of the packet request frame arrive, they are also read from the output of node 77 (Fig. 6) at the address given by element 50 to the address trunk by reading the address from the translation area specified in the RAM. In this area, depending on the value of the address of the received frame and the state of the module of the primary station 9, one of three further broadcast addresses can be found:

A. The address of the operative pavilion area is alternative A, Module 10 at station 2 will process this frame, as in the prototype, and the result of processing will be output under control of unit 11

15 to the interface unit 6 and further to the data terminal equipment set. This result is nothing more than a Call Request - Incoming Call packet.

20 A set of 4 terminal equipment of station 2 data — the initiator of the test, having received an incoming call into the packet, transmits through the gateway 6 packet the call is accepted using

thirty

35

40

m ti 8, where the buffer and the program are located are the same logical channel as the packet of the station (when we decode our address);

B, Address of the input register of node 77 (Fig. 6) when decoding another address in the frame and the passive state of the primary station;

B. Address of the RAM area 8, where the transit buffer memory module 28 (FIG. 1) is located, when deciphering the foreign address and the active module 9 of the primary station.

In case A, the received frame is addressed to the given subscriber (data terminal equipment) and is processed in block 10.

In the case of. B, the received frame is not addressed to this station 3 and is relayed from the output register 77 of the node to the input register of the same node, then goes to transceiver 75 (FIG. 6), where it is converted into sequential form, and through element 80 with joint C2 comes at the junction C2 of the modulator 12 and further into the outgoing channel and the demodulator 13 of the data station 2. Address analysis in block 29 of the translation shows that this is your address, and alternative A. is in place.

In case B, the element 50, after completion of the output to the modulator 12 of the frame of the primary station, puts the module 9 of the primary station into the passive state. This is recorded in the broadcast unit by the decoders and output trigs Input w 1st call. In this case, the logical channel is transferred to the state Data transfer,

Transmission of the response packet The call is received in the same way as the transmission of the request packet. The call request. As a result, the data terminal equipment kit — the test initiator — receives an incoming packet. The connection is established with the same logical channel number that was specified in the Call Request packet, and this logical channel is also fully switched to the Data Transfer state in the virtual connection. Package format Call Received

 shown in Fig.8. In a virtual independent test connection, there can be an unlimited time for transmitting 5 data packets with the format shown in FIG. 9. At any time, a set of data terminal equipment can complete the testing procedure by passing through packet conjugate block 6 a request for termination of the DTE. In this case, the logical channel is placed in the Request for Termination state of the DTE. When the data channel equipment set is ready to release the logical channel, it, under the control of unit 11, transmits through the interface unit 6 a packet Confirmation of the completion of the set of DCE, which defines the same logical channel, which then

55

39 and 40. As a result, the signal from the output of the AND 44 element is given permission to read the contents of the encoder 48, which is the driver of the read pointer from the block 28 of the delayed test frame. This delayed frame has the data staggy address 2, as a result of which

at this station in the broadcast unit

Alternative A, Module 10 at station 2, will process this frame as in the prototype, and the result of processing will be output under control of block 11

in block 6 of the interface and further in the set of data terminal equipment. This result is nothing more than a Call Request - Incoming Call packet.

The set 4 of the terminal equipment of the station 2 data - the initiator of the test, having received the incoming call into the packet, transmits through the gateway 6 packet the call is accepted using

same logical channel as the packet

Login w 1st call. In this case, the logical channel is transferred to the state Data transfer,

Transmission of the response packet The call is received in the same way as the transmission of the request packet. The call request. As a result, the data terminal equipment kit — the test initiator — receives an incoming packet. The connection is established with the same logical channel number that was specified in the Call Request package, and this logical channel is also fully switched to the Data Transfer State in the virtual connection. . Package format Call Received

shown in Fig.8. In a virtual independent test connection, there can be an infinitely long transmission of data packets with the format shown in FIG. 9. At any time, a set of data terminal equipment can complete the testing procedure by passing through packet conjugate block 6 a request for termination of the DTE. In this case, the logical channel is placed in the Request for Termination state of the DTE. When the data channel equipment set is ready to free the logical channel, it, under the control of unit 11, sends a packet via the interface 6 block Confirmation of the completion of the set of DCE, which defines the same logical channel that

is in Ready state for occupation. Packet Formats Request completed, Confirmation of completion is shown in Figures 10 and 11.

If, in the process of exchanging frames with test information, at station 3, situation B occurred in which the primary station was engaged in transmitting a frame of a given station, the test frame is recorded in the module of the transit buffer memory 28 (Fig. 1). As soon as the primary station goes into the passive mode, it is recorded in the translation unit 29 by the decoder and output triggers 39 and 40. As a result, signal from the output of the element 44 gives permission to read the contents of the encoder 48, which is the driver of the read pointer from As the 28 delayed test frame, It has the address of the station 2 data, as a result of which the analysis of this station in the broadcast unit 29 revealed alternative A, the module 10 at this station processes the test frame and the result of the processing in the form of The corresponding packet is outputted through block 6 to the set of terminal equipment. The data initiator is the test initiator. Next, the testing process continues as described above;.

Thus, the set of data terminal equipment — the initiator of testing — receives test packets in the form in which it transmitted along the chain: module 9 of the primary station, modem of station 2, outgoing channel, incoming channel of station 3, set of equipment of the data channel of station 3 , outgoing channel, incoming channel of station 2, demodulator, module 10 of station 2, block 6 — set of data terminal equipment — test initiator. At the same time, the set of terminal equipment of station 3 data is not involved in the testing process. Obviously, similarly to the described, data can be simultaneously tested by both stations.

Claims (1)

Invention Formula A device for interfacing a subscriber with a communication channel, comprising a communication unit with a subscriber, a program and data memory, a random access memory, a control unit, a communication unit with a modem, a modulator and a demodulator, the group subscriber communication unit I / O is a group of device I / O units for connecting to subscriber I / O, data I / O, address, gating, and receiving permission / control unit outputs are connected to data input / output, address, gating, and . enabling the reception of the communication unit with the subscriber, the program memory and data, the RAM and the communication unit with the modem; the output of the issuance of the issuance of the control unit is connected to the enable inputs of the issuance of the communication unit with the subscriber, the RAM and the communication unit with the modem, the output of the memory address of the control unit is connected to the input of the selection of the memory area of the main memory; the output of the enable resolution of the control unit is connected to the enable input of the interrupt of the communication unit c. the modem, the output of the exchange of the block — communication with the subscriber is connected to the reset inputs of the control unit and the communication unit with the modem, the interrupt request output of which is connected to the same input of the control unit, the capture input of which is connected to the output of the readiness memory, the first and The second line inputs / outputs of the communication unit with the modem are connected respectively to the first inputs and outputs of the modulator and demodulator, the second inputs and outputs of which are the input outputs of the device for connection to the communication channel, distinguishing With the aim of increasing testability and reducing the fault localization time, a translation block is inserted into it} containing three buffer registers, a decoder ibipe, four flip-flops, four AND elements, four encoders and an OR element, and the input-output buffer the registers are connected to the input-output of the command data of the control unit; the enable inputs of the first, second and third buffer registers are connected to the output of the address of the control unit; the gates of the first, second and third buffer registers, the first input s first to fourth .deshifratorov and the first to fourth encoders connected to the output of the gating control unit, inputs of the first recording, second and third buffer registers, the second inputs of the first to fourth deshif13 Ratio: encoders, first inputs from the first to the fourth, And elements are connected to the output resolution at-. The control unit, the read inputs of the first and second buffer registers and the third inputs, from the first to the fourth, of the decoders are connected to the output of the output of the output of the control unit, and in the translation unit, the output of the first buffer register is connected to the fourth inputs of the first and second decoders, the output of the second buffer the register is connected to the fourth inputs of the third and fourth decoders, the output of the first “decoder I is connected to the first installation inputs of the first and second triggers, the second installation inputs of which. connected to the output of the second decoder, the output of the first trigger is connected to the second input of the first element, the output of which is connected to the third input of the first encoder, the output of which is connected to the first input of the eleg P V w w g j  В 1о I --- --j - - I / V / rvv 7 7 sixteen L J8 11 nineteen 22 U . n 08225 14 ten 15 20 25 ment W1I, the output of which is connected to the information input of the third buffer register, the output of the second trigger is connected to the second inputs of the second and third elements I, the outputs of which are connected to the third inputs of the second and third encoders and the first and second installation inputs of the fourth trigger, whose output is connected the second input of the fourth AND element, the output of which is connected to the third input of the fourth: encoder, whose input is connected to the second input of the OR element, the output of the third and fourth decoder Ina with the first and second installation inputs of the third trigger, the first and second outputs of which are connected respectively to the third input of the second, element And and the third, inputs of the third and fourth elements And, the outputs of the second and third encoders are connected to the third and fourth inputs of the element OR. 29 Sh / 3 20 21 12 CfJUf.l fie. (rigging srig, 6 bits d Octets one Faye. 7 FIG. at bits and Octets ffi / m d bits 8 FIG. 9 FIG. ten