SU1501255A1 - Pulsed phase detector - Google Patents

Abstract

The invention relates to radio engineering and can be used in devices with a PLL. The purpose of the invention is to reduce output ripple at a reference frequency. The detector contains a stable current generator 1, charge and discharge switches 2, 4 charge cond-p 3, source repeaters 5, 7, 13 voltage, storing cond-p 8, cond-9, RS-trigger 10, element I -NON 11, delay element 12, diode 14. To achieve the goal between the trigger input 10 and the control input of the key 4, an element 16 was entered, and a delay element 15 was entered. After the pulse signal arrived at the detector signal input on the cond 3, a signal is generated trapezoidal shape, the amplitude of which is directly proportional to the phase difference of the reference and measured with analogs, and the length of the trapezoid vertex has a constant value equal to the total delay of the delay elements 12 and 15, which ensures a reduction in the level of the pulsations with the frequency of comparison at the output when the phase difference of the input signals is close to 180 °. 2 Il.

Description

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SL SP

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3130

The invention relates to radio engineering and can be used in devices with a phase-locked loop.

The purpose of the invention is to reduce output ripple at a reference frequency.

Lig.1 shows the structural electrical circuit of the pulse-phase detector; on Lig.2 - time diagrams of his work,

The pulse-phase detector contains a stable current generator 1, a charge switch 2, a charge capacitor 3, a discharge switch 4, a first source voltage follower 5, a sample switch 6, a second source voltage follower 7, a storage capacitor 8 , capacitor 9, RS flip-flop 10, element AND-NOT 11, first delay element 12, third source voltage follower 13, diode 14, second delay element 15, And element 16.

Pulse-phase detector works as follows.

When a pulse signal is received}) ig.2a, with a logic zero level, the reference input of the detector RS-flip-flop 10 is set to one state of FIG. 2d, and the discharge key 4 is opened, ensuring the discharge of the charge capacitor 3 to zero potential of FIG. 2g. During the time of the pulse at the reference input of the detector, a single level signal (}) ig.2d is generated at the output of the element NE-NE 11, which arrives at the control input of the charging switch 2 and closes it. After the input impulse of the reference signal is terminated, a logical zero signal is generated at the output of the NAND 11 element, which opens the charging key 2, and the signal of the FIG. 2 logical unit that closes the bit 4 With an open charge switch 2, the charging capacitor 3 is charged by the stable current generator 1, As a result of the charging of a stable current, the increasing linear sawtooth voltage of FIG. 2g is formed on the charging capacitor 3, the maximum value It corresponds to the phase difference of the input signals equal to 360 bcf.

five

0 s about 5

0

When a pulse arrives in Fig. 2b with a logic zero level at the signal input of the pulse phase detector, the RS flip-flop 10 is set to the zero state, and a signal is generated at the output of the I-M1 1 1 element. l with the level of the logical unit that closes charge key 2. At the same time, the bit key A is also in the closed state. The closed state of both switches ensures the fixation of a constant voltage on the charge capacitor 3 of Fig. 2g, which is equal in size to the sawtooth signal at the moment of arrival of the pulse to the signal input of the pulse-phase detector.

Thus, when a pulse signal arrives at the detector signal input, instead of a sawtooth signal, a trapezoidal signal is formed on the charged capacitor 3, the amplitude of which is directly proportional to the phase difference of the reference and measured signals.

The constant voltage, fixed to the charged capacitor 3, through the first source follower of the voltage 5 of Fig. 2c is fed to the input of the sampling key 6. To the control input of the sampling key 6, through the first delay element 12, the pulse signal of Fig. 2b is received at the signal input of the detector. This signal opens the sampling key 6 and through the first source voltage follower 5, the storage capacitor 8 is charged until the voltage is fixed to the charging capacitor 3. The signal in the form of a constant voltage of FIG. 2i on the storage capacitor 8 through the second source voltage follower 7 enters the output device. Simultaneously with the charge of the storage capacitor 8, the third source voltage follower 13 charges the charge of the capacitor 9 also before the fixation voltage of the charge capacitor 3. The first delay element 12 provides the opening of the sampling key 6 after the change of the voltage on the charge capacitor 3 ends. the delays of the first delay element 12 must be greater than the total switching time of the RS flip-flop 10 and the charging switch 2. The introduction of the sampling delay together with the fixation eg 5

It is possible to change the voltage at the key input (part B1,1 of the sample during the sampling process).

The pulse signal from the output of the first delay element 12 also enters through the second delay element 15 to the second input element AND 16. In this case, a zero level signal is generated at its output, which opens the bit A, and produces a discharge of the charge capacitor 3 to zero potential. The delay of the second delay element 15 must be greater than the total sample time and the switching time of the key 6 sample.

Thus, after the pulse signal arrives at the detector signal input, a trapezoidal signal is formed at the charge capacitor 3, the amplitude of which is directly proportional to the phase difference between the reference and measured signals, and the length of the trapezium verpeena has a constant value equal to the total delay of elements 12 and 15 that provides a reduction in the level of ripple with a frequency of comparison at the output when the phase difference of the input signals is close to 180 °.

With the arrival of the next pulse and reference input of the detector, the process described above repeats, however, the waveform at the output of the first source voltage repeater 5 may differ from the waveform of the charged capacitor 3 due to the action of the nonlinear feedback circuit on the third a voltage source follower 13, a capacitor 9 and a diode 14. This feedback circuit provides a correction for the amplitude and shape of the keystone signal at the output of the voltage source repeater 5, depending on the voltage on the capacitor 9, equal to the voltage on the storage capacitor 8, i.e. depending on the magnitude of the phase difference between the reference and the measured

556

the signal recorded by the detector in the previous measurement period.

Thus, in the stationary mode, when the phase difference between the reference and measured signals is constant, a keystone signal is received at the input of sample key 6 with a level difference equal to U and a duration equal to the total delay of elements 12 and 15, i.e. G, (fig.2z),

For this signal, approximated by rectangular pulses, using the Fourier decomposition, we obtain the amplitude of the first harmonic of the output signal with the frequency of comparison at the input of sample key 6

2U4. (T -1)

and - - sin.

I ex IIt

where c ,, is the duration of the output signal of the (logical) element 11 NAND, during which the charge key 3 is open, But is the direct voltage drop

on diode 1A,

accordingly, the amplitude of the first garonics at the output of key 6 of the sample will be equal to

- Ears With 12ysC K ". f (T; 2i)

Sk.-y

(c. l + c.)

singde - key capacity 6

sampling,

Claims (1)

Cg is a storage capacitor capacity 8. Formula of the invention Pulse-phase detector avt.Sv. No. 1A37963, characterized in that, in order to reduce output ripple with a comparison frequency, an element I is inserted between the S-input of the RS flip-flop and the control input of the bit switch, between which the second input and the output of the first delay element is entered the second delay element. and ainr u u f t tu and .ЛГ “: Jl u J Tf / Jl u IT IL IT ZTGCH ic; ЗЦ T-tl o, Phage.1