SU1495849A1 - Memory - Google Patents

Abstract

The invention relates to computing, in particular, to storage devices with electrical erasure and preferential reading of information, and can be used as part of specialized digital computers or data processing systems as a non-volatile information carrier. The aim of the invention is to increase the reliability and enhance the functionality by providing automatic erasure before writing, reading information in the recording mode and monitoring the reliability of the recorded information in the recording mode. The device contains a memory block, a control block, a page register, a page address counter, an address register, an address-latch register, a sample decoder, a read register, a write register, a transceiver unit, a high voltage driver, a comparison unit, and the first and second error detection units , an error signal generator and a multiplexer unit. The purpose of the invention is achieved by the fact that during the erase cycle, data is written and read from the erasable page, which is firmware loaded into the page register. 29 il.

Description

The invention relates to computing, in particular, to storage devices with electrical erasure and advantageous reading of information, and can be used in specialized PPMs or data processing systems as a non-volatile information carrier.

The purpose of the invention. Improving the reliability and expanding the functionality by providing automatic erasure before writing, reading information in the write mode and control of reliability

recorded information in recording mode.

FIG. 1 shows a diagram of a storage device; in fig. 2 is a control block diagram; FIG. 3 shows a state register; in fig. 4 is an interface block diagram; in fig. 5 is a diagram of a clock generator; in fig. 6 is a diagram of the first and second synchronizers; 7 is a frequency divider circuit; in fig. 8 is a diagram of the first register of microinstruction addresses; in fig. 9 is a diagram of the first control ROM; in fig. 10 - the scheme of the first register of microinstructions; on

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ig. 11 is a loop counter diagram; on ig. 12 is a diagram of a second register of microinstruction addresses; FIG. 13 is a diagram of a second control ROM; on Fig.14 is a diagram of the second register of microinstructions; in fig. 15 and 16 are diagrams of a memory block; FIG. 17 is a page register diagram; FIG. 18 is a diagram of a page address counter; in fig. 19 is an address register map; in fig. 20 is a schematic of an address latch register; in fig. 21 is a sample decoder circuit; Fig 22 is a register register; in fig. 23 -. register register; Fig, 24 is a block diagram of transceivers; in fig. 25 is a high voltage driver circuit; Fig. 26 is a block diagram of the comparison; Fig. 27 is a diagram of the first and second error detection units; on Fig diagram of the driver of the error signal; in fig. 29 is a block multiplexer diagram.

A storage device (FIG. 1) 25 ROMs (SHS) 93 and 94 with load resistors and a resistor 95.

UepBt register 30 micro-commands (Fig. 10) contains register chips 96-99 with a total synchronization of 30 and reset on the basis of D-flip-flops.

The counter 32 cycles (Fig. 11) contains the chips of binary counters 100 and 101 and the resistor 102.

The second register 33 of the microcosm contains a memory block 1, a control block 2, a page register 3, a page address counter 4, an address register 5, an address register latch 6, a sample decoder 7, device address inputs B, a register 9 reading, register 10

records, unit P transceivers,

high voltage driver 12,

block 13 comparison, first block 14

error detection, the second block 15 35 (Fig. 12) - contains binary digits

error detection, shaper 16 three-bit counters 103 and 104 with

an error signal, a multiplexer block 17, a device write input 18, a device read input 19, a device ready output (ready / busy) 20, a device fault output 21,

The control unit 2. (FIG. 2) contains a state register 22, a mate unit 23, a clock generator 24, a first synchronizer 25, a frequency divider 26, a second synchronizer 27, a first microcommand address register 28, a first control ROM 29 (OT13U 1 ), the first register of 30 micro-instructions, trigger 31, the counter of 32 cycles, the second register 33 of the addresses of micro-instructions, the second control ROM 34 (ROM 2), the second register of 35 micro-instructions.

The state register 22 (FIG. 3) contains a recording latch 36, a reading latch 37, a lock trigger 38, a secondary write trigger 39, an AND 40 element, a page address trigger 41, a comparison circuit trigger 42, a counter preset and reset trigger 43, and a resistor 105 .

UZU 2 34 (fig. 13) contains BIS 40 ROM 106 with load resistors and resistor 107.

The second micro-command register 35 (FIG. F4) contains register chips 108 and 109 with common synchronization and reset based on D-flip-flops.

Memory block 1 (Figs. 15 and 16) contains To the LSI triads of reprogrammable permanent storage devices 110-112 with electric erasure (EEPROM), majorization elements 113 and n triads 2I-HE 114116, with Kg, where n - resolution of the device; b - BIS EEPROM size,

Page register 3 (FIG. 17) contains To BIS I17 two-address general-purpose registers with two

50

l, 44 idle trigger, 45 erase trigger, 46 rewriting trigger, OR elements 47–49, control outputs 50–60,

Interface unit 23 (FIG. 4) contains AND 61-65 elements, AND-NE 66-69 elements, OR elements 70-78, and HE elements 79 and 80,

The clock generator 24 (FIG. 5) contains elements GEGE 81-83, resistors 84 and 85, and quartz resonator 86. The first 25 and second 27 synchronizers (FIG. 6) contain an element E 87 and a D-flip-flop 88.

The frequency divider 26 (FIG. 7) is a series-connected D-flip-flops 89 and -90.

The first register 28 of microcommand addresses (Fig. 8) contains a binary four-bit counter 91 with presetting and resetting and a resistor 92,

ESS1 1 29 (Fig. 9) contains LSI

preset and reset and resistor 105.

UZU 2 34 (Fig. 13) contains BIS ROM 106 with load resistors and resistor 107.

The second micro-command register 35 (FIG. F4) contains register chips 108 and 109 with common synchronization and reset based on D-flip-flops.

Memory block 1 (Figs. 15 and 16) contains To the LSI triads of reprogrammable permanent storage devices 110-112 with electric erasure (EEPROM), majorization elements 113 and n triads 2I-HE 114116, with Kg, where n - device depth; b - BIS EEPROM size,

Page register 3 (FIG. 17) contains To BIS I17 two-address general-purpose registers with two

51

I / O ports and a resistor 118. The counter 4 of the page address (Fig. 18) contains a binary four-bit counter 119 with presetting and resetting.

The address register 5 (FIG. 19) contains 1 register chips 120 with common synchronization based on D-flip-flops.

The register-latch 6 address (Fig.20) contains a register chip 121 and 122 with a common synchronization based on D-flip-flops.

The decoder 7 sample (Fig. 21) contains a binary decoder 123 type 3-8.

The reading register 9 (FIG. 22) contains To dual channel multiplexes 124 with embedded registers on the output.

Register 10 entries (Fig. 23) contains m register chips 125 with a total synchronization based on the D-three

gerov.

The transceiver unit 11 (FIG. 24) contains an element NOT 126, elements 2I-NO 127-129 with an open collector and To chips of transceivers 130.

The high voltage driver -12 (Fig. 25) contains the elements HE 131 and 132, the registers 133-138, and the transistors 139-141.

Comparison unit 13 (FIG. 26) contains g elements INEQUALITY 142 and AND-NO element 143, where g is the page address width.

The first 14 and second 15 error detection blocks (Fig. 27) contain S chips 144 of the parity generator and the element UNEMINABILITY 145.

The driver 16 of the error signal (Fig. 28) contains n elements UNEQUAL, 146, the element OR 147, the D-trigger 148 and the element And 149.

The multiplexer block 17 (FIG. 29) contains K dual channel multiplexers 150.

The device works as follows.

When the power supply is turned on, all the registers are reset (the power-on reset circuit is not shown).

In the read mode, after the occurrence of the address signals and readings on the corresponding inputs of the device, the decoder 7 of the sample allows operation

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That block 2 controls set

five

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The read latch 37 and the blocking trigger 38 of the state register 22 are set to high state G, the Ready ready / busy signal is set at the device output 20, the first register 28 of the microinstruction address is reset to zero and the clock output from the clock generator 24 is reset via the first synchronizer 25 to the input of the sequential account of the first register 28 of the micro-command address and the load input of the first register of the 30 micro-commands; The address code is also loaded into the address register 5 and the address-latch register 6. In this case, the register-latch 6 of the address is latched due to the fact that its load input is connected to the output of the trigger 41 of the address of the page of the state register 22. Signals from the state register 22 per input group of the EEPR1 29 determine the area of the readout firmware addresses. The control signals set by the firmware, through the first register 30 of micro-instructions and the block 23 of the conjugation, arrive at the corresponding nodes of the device. The higher address bits (page address) are fed to the inputs of memory block 1 from the address-latch 6 address. In the first micro-command of the read firmware, the lower-order address bits are loaded into the counter 4 page addresses and fed to the block 1 of the memory. Then, signals corresponding to the read mode (chip sampling and read resolution signals) are generated and supplied to the memory unit 1. Simultaneously, the first error detection unit 14 monitors two incoming address codes modulo. In case of an error, a malfunction signal is generated, which through the transceiver unit 11 arrives at the device fault output 21.

After the sampling time of the EEPROM microcircuit chips used in block 1, read signals are taken and the read register 9 is loaded, the input group of which is supplied with data read from memory block 1. After the reading register 9 is loaded, the data is received through the transceiver unit 11 to the information inputs and outputs of the device and simultaneously to the second error detection unit 15, which controls modulo two incoming information and in case of an error produces a fault signal through the transceiver unit 11 arrives at the output 21 of the fault device. Since the read information comes from the memory block 1, the majority elements of which correct all single errors of the elementary bits corresponding to the various bits of the data word, the second error detection block 15 detects all the single errors in the data word that can be caused by multiple bits in the elementary the bits of memory block 1 and the error probability of a higher order is low. Then all enabled device registers are reset. The device is ready for the next call.

In the recording mode, after the recording signals, addresses and input information on the corresponding inputs of the device, the sampling decoder 7 enables operation; the control unit 2 is set to high state 1 recording latch 36 and lockout trigger 38 of the state register 20 the Ready ready / busy signal is set, the address register 5 is loaded, the address-latch register 6 and the record register 10 are loaded. At the same time, the first register 28 of the micro-command addresses and the first register of the 30 micro-commands are reset to zero and the sync pulses from the clock generator 24 output through the first synchronizer 25 to the corresponding inputs of the first micro-command register 30 are allowed. The signals from the status register 22 per group of inputs of the EEPR1 29, define the area of the firmware address, page read.

At the same time, the address of the read page is determined by the register status of the address latch 6. The firmware reads the data from memory block 1 when the page address counter 4 is zero, loads it into read register 9, then writes this data to page register 3 via the first I / O port. Next, the counter 4 page addresses are incremented and the first re is reset.

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gist 28 micro-command addresses and the first register of 30 micro-commands. The described firmware section is repeated. Thus, a cyclic rewriting of a page of information from memory block 1 to page register 3 occurs. After rewriting the last word of the page and incrementing counter 4 of the page address by overflowing the last one, the microclimate program is exited. The overflow signal of the counter 4 of the page address through the interface block 23 is fed to the input of parallel loading of the first register of the microcommand address 28, loading the transition address, after which the lower bits of the address received from the address from register 5 are written to the counter of the 4 page address. Then at this address the information from register 10 of the record is entered into the page register 3 via the first I / O port. The erase trigger 45 and the idle trigger 44 are set and the state register trigger 22 is reset, and the Ready / busy lock signal is removed from the device output 20. Thus, in the page read firmware, the data page is overwritten from memory block 1 to the page register 3 and its modification in accordance with information received in register 10.

After installing the erase trigger 45, the clock pulse is allowed to pass through the frequency divider 26 and the second synchronizer 27 to the corresponding inputs of the trigger 31 and the second register 35 of micro-instructions. The direct output of the trigger 31 is connected to the low-order bit of the address of the UPZU2 34, and the inverse output of the trigger 31 through the counter 32 cycles to the serial input of the second register 33 of the address of the microinstructions. Switching the lower bit of the address of the UPZU2 34 and the incrementing of the cycle counter is due to the fact that in one of the data bits U113U2 34 zeros O and 1 are alternately recorded. I As a result, for each sync pulse, the information in this bit connected to the information input of the trigger 31 is changed, causing the latter to switch. The increment of the second register 33 of the microinstructions is carried out on the overflow

The counter counts 32 cycles. Such an organization allows the processing of long time diagrams and the Signal coming from the state register 22 to the input of the higher bit of the EPROM address 34 determines the address area of the erasure firmware. After the idle trigger 34 has been installed, the signals from the state register 22 to the input protection group 29, determine the address area with idle microcommands, i.e. There are no control signals at the output of the first register of 30 microcommands.

From the output of the second register of 35 microinstructions, the block 1 of memory receives, through the block 23, the signals of sampling, recording resolution, and erasure. The high voltage driver 12 generates a high voltage pulse, and in memory block 1, the page is erased at the address specified by the address latch 6 of the address. Since the erase process takes quite a long time (from tens to hundreds or more milliseconds for different BIS EEPROM), it is allowed to access the device after the end of the microprogram of the page readout and the start of the erase microprogram.

When reading, the idle trigger 44 is reset, the address register 5 is loaded and set

There is a read latch 37 and a state register trigger lock 38 of the 22 state. At the output 20 of the device, a ready signal appears Ready / occupied. Initiates the execution of the secondary reading firmware. In this case, the comparison unit 13 performs a bitwise comparison of the states of the latch 6 of the address and the corresponding bits of the register 5 of the address. In case of a mismatch, the unit 1 value of the signal from the output of the comparison unit 13 is fed to the information input of the trigger 42 of the comparison circuit of the state register 22, and the first microcommand triggers this trigger, as a result of which the code to the address input group of the UPZU1 29 determines the area of the microprogram address setting trigger trigger 44 idle. In doing so, the lock and trigger trigger 38 of the state register reading 22 remains cocked.

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20 25

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If the address codes loaded into the address register 5 and the address latch register 6 coincide, when a zero level O signal O is set at the output of the comparison block 13 and the comparison circuit trigger 42 is not activated, the secondary read microprogram microcode loads the lower 4 address into the counter 4 address bits from address register 5, then the corresponding signals are generated to read the data word from page register 3 through the second I / O port. The read word is loaded into the reading register 9 and through the transceiver block 11 enters the information inputs / outputs of the device. At the same time, the blocking trigger 38 signal is ready Ready / occupied at the output 20 of the device and the read latch 37 is reset, the idle trigger 44 of the state register 22 is set.

At the same time, the erase firmware either continues to run or is terminating and the device waits for the next access.

When accessing the record at the time of erasing, the record latch 36 is already cocked, therefore trigger 39 is reset, secondary readout trigger 38 is ready / occupied at device output 20, idle speed trigger 44 is reset, status register 5 is loaded, and the write register 10, at the beginning of a call, the first register 28 of the micro-instruction addresses and the first register 30 of the micro-instructions are zeroed. The word of the state, coming from the state register 22 to the address entry group of the EEPR1 29, defines the address area of the secondary recording firmware. A comparison circuit trigger 42 is loaded, and if it is set (register 3 codes and latch 6 addresses of the address do not match), the output of the state register 22 is a code defining the address area of the microprogram, resetting the secondary recording trigger 39 and setting the trigger 44 register of 22 states. In this case, the blocking trigger 38 by the ready signal Ready / occupied at the output 20 of the device remains cocked.

If the microcommand for loading the trigger 42 of the comparison scheme does not cock it.

those. the address is made to the same page that is currently being processed, the lower bits of the address from the address register 5 are loaded into the page address counter 4, and signals for recording information from the register 10 writing to the page register 3 are generated through the first I / O port.

Then the secondary recording trigger 39 is reset, the lock trigger 38 is set, the idle trigger 44 is set, and the device waits for the next call.

At the end of the erase firmware, a rewrite trigger 46 is set, the erase trigger 45 is reset, i.e. the synchronization pulses through the second synchronizer 27 are prohibited to the corresponding inputs of the trigger 31 and the second micro-command register 35, and the second micro-command address register 33, the 32-cycle counter and the second micro-command register 35 are zeroed. The device is waiting for the next access. In the case when the access occurs to the same page, whose address is latched in the address latch 6, the firmware of the secondary reading or secondary writing is processed, and access is made only to the page register 3. When turning to another page, the erase trigger 45 and the trigger are reset 44 of the idle state of the 22 state register, the synchronization of the clock pulses through the second synchronizer 27 to the counting inputs of the trigger 31 and the second register of the 35 microcommands is allowed. The signal from the register of 22 states to the input of the high-order bit of the address of the EEPR2 34 (coded rewriting trigger 46) determines the area of the rewriting microprogram addresses.

In the rewrite firmware, the write enable signals for memory block I are generated, the high voltage former 12 is not generating programming voltage pulses, the sample enable and read enable signals to page register 3 are sent to read data through the first input-output port and feed them as input to memory block 1.

At the same time, on the memory block 1, the higher bits of the addresses defining the address

five

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five

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pages, served from the address-latch register 6, and the low-order bits of the address are fed simultaneously to the memory block I and page register 3 from the page address counter 4, with the rewrite firmware starting from the zero value of the page address counter 4. Upon completion of the rewriting of a word with a zero address inside the page from page register 3 to memory block 1, the counter of the 4 page address is incremented and the second register 33 of the microinstruction addresses is reset, the counter of 32 cycles and the second register of 35 microcommands, i.e. returns to the beginning of the firmware with the new value of the address inside the page. When the last word of the page is rewritten, the counter of the 4 page address is overflowed. The overflow pulse through the interface unit 23 loads into the second register 33 of the micro-command addresses the transition address and, thus, initiates the exit from the cycle to the line-. rewrite firmware portion. Next, idle commands (no control signals) are generated to form the exposure time before re-writing, the duration of which is specified by the technical conditions for this type of BIS EEPROM. Then, the control trigger 43 is set, the overwrite trigger 46 is reset, the erase trigger 45 and the idle trigger 44 of the state register 22, reset the second register of micro-instructions 33, the counter of 32 cycles, the second register of 35 micro-commands. The signals from the state register 22 to the input group L13U1 29 determine the region of the control firmware,

In the contro firmware)) ol, the page address counter 4 is assigned a zero value, and the sample and read resolution permits for memory block 1 are generated. The read word is loaded into the read register 9. At the same time, signals are being produced to enable the sample and readout of the data word from page register 3 via the second I / O port. The information from the reading register 9 is fed to the first group of inputs of the error signal generator 16, and the information from the page register 3 to the second rpyji input of the block 16. Block 16 performs a bitwise comparison, and in case of a mismatch at least one bit, the latch fails - correctness (D-flip-flop 148, element And 149).

Then the counter 4 of the page address is incremented, the first register 28 of the micro-instruction addresses and the first register 30 of the micro-instructions are zeroed, and the process is repeated cyclically until the counter 4 of the page address, i.e. the whole information of the newly recorded page is compared with the contents of the paging register. After the counter 4 address of the page overflows, the control firmware exits the cycle (the counter of the address of the page 4 overflows through the interface block 23 loads the transition address into the first register 28 of the microinstruction addresses) the page address trigger 41 is reset, then the page address trigger 41 is reset, i.e. The new address of that page is loaded into the register-latch 6 of the address, the call to which initiates the rewrite firmware. At the same time, the comparison circuit 42 is triggered and the state register trigger 22 is triggered 43.

If a new page initiating the rewrite firmware is accessed by writing, then the register 28 of the micro-command address and the first register 30 of the micro-command are reset to zero and the page is read. The processing of a new page by post begins.

If a new page initiating the rewrite firmware is accessed by reading (read latch 37), resetting the write termination 36 is reset, resetting the first register 28 of the microinstruction addresses and the first register 30 of the microinstructions and resetting to the readout microprogram. Upon completion of the read firmware, all the involved registers are zeroed out and the device returns to its original state.

The use of a microprogram control unit provides greater flexibility of the device and allows using any TI-nominal BIS ESPROM in the memory block, as well as organizing various control and diagnostic checks at the microprogram level.

Erasing is done automatically in recording mode, while erasing information is stored in the page register. Overwriting in the memory block occurs only after modifying the entire page or when accessing another page. In the write cycle, the paginal data is available to the user. Such an organization improves the performance of the proposed device, as well as saving erase-write cycles.

The reliability of the recorded data is monitored in a write cycle by reading information from the memory block and comparing it with the contents of the page register.

Claims (1)

Invention Formula A memory device containing a memory unit, a control unit, the first output of which is connected to the control input of the transceiver unit, whose information outputs are connected to the information inputs of the write register, and the information inputs are connected to the outputs of the reading register, the information inputs of the first and second groups of which are connected to the outputs of the page register and the memory block, the power input of which is connected to the output of the high voltage driver, information inputs and address inputs of the primary the memory unit groups are connected respectively to the input-outputs of the page register and to the direct outputs of the address-latch register, the information inputs of which are the address inputs of the first group of the device, and the synchronous input is connected to the second output of the control unit, the outputs of the first, second and third groups connected to the control inputs of the page register, the reading register and the memory unit, the third and fourth outputs of the control unit are connected respectively to the control input of the high driver on yarn and sync register register, the first and second inputs and the fifth output block Controls are respectively the write and read inputs and the device ready output, the control output of the transceiver unit is the output of the device malfunction, in order to increase reliability and expand the functional transition of the control unit, the mode setting input and the outputs the fourth group of which is connected respectively to the overflow output and to the control inputs of the page address counter, whose information outputs are connected to the address inputs of the second group s of memory and hell Possibilities due to provision of page registers with automatic entries. 1higher erasure before recording, O-reading information in recording mode and monitoring the reliability of recorded information in recording mode, c) the first and second error detection blocks, the multiplexer unit (hypersors, comparison unit, page counter, address register, de- The sampling digitizer and the error signal generator, the sampling decoder inputs are the address inputs of the second group of the device, the sampling distributor output is connected to the control unit resolution enable input (the output of which is connected to | This is the address register, whose information inputs are connected to the address inputs of the first group of the device, and the sensors are connected to the inputs hepBoro error detection block, the second group modes and the outputs of which At the inputs of the counter of the address of the page and to the inputs of the first group of the comparison unit, the inputs of the second group and the output of which are connected respectively to the inverse outputs of the register, the informational inputs-outputs of the mouth address latches and a sign input roystva information inputs of the first group of multiplexers are connected to the outputs of the reading register, to the inputs of the second error detection unit and to the information inputs of the first group of the error signal generator, informational inputs of the second group, the control input and output of which are connected respectively to the outputs of the page register, the seventh output of the block control and with the first input of the error sign of the transceiver unit, the second and third inputs of the error indication of which are connected to the outputs of the first and second blocks, respectively error detection, the outputs of the fifth group of the control unit are connected to the control inputs of the multiplexer unit, the information inputs are connected respectively to the outputs of the write register and the inputs / outputs of the page register, the input outputs of the transceiver unit are roystva Phie.) tmh.J Yt1l 1} ff Omftk Phi z KfflS  3V Phie. FI.5 Phie.in K5A.25 - Theb.7 Phie.in FIG. YU FIG. eleven FIG. 12 K5l.35 fie. 13 FIG. / Fi8. /five KffA.c.,; FIG. 18 one Phie. J9 From 5l Phie.GO yes Cr -Nuf rr-v, tS Se Thebes. 22 HOTEL.5 Thebes. 2 495849 .i FIE 21 YU  Sh KSA.17 From 5 years FIG. 23 OmSA.sl G-. From L |. 6 From SA. 5 (9)  JUyLJ -r  : FIG. 25 Fi.26 iG Jits Q.P. - Fie.27 . 28