SU1494197A1 - Device for control of stepping motor - Google Patents

Abstract

The invention relates to electrical engineering, in particular, to controlling a four-phase stepper motor in the electric crushing mode of the main step, and can be used to control equipment equipped with a stepper motor. The purpose of the invention is to simplify and improve reliability. The device contains permanent memory devices 1, 2 of the same capacity, address inputs connected to counter 3, and outputs to the inputs of corresponding digital-to-analogue converters 4, 5 with polarity setting devices 6, 7 connected to inputs of controlled current stabilizers 8, 9. Counter 3 has the number of bits one more than the number of working address inputs of permanent storage devices 1, 2, and the output of the counter connected to the higher address input of the permanent storage device is connected to one of the inputs of the AND element Plug or 10 and the next significant bit of the counter - to the second input of the EXCLUSIVE OR gate 10 and to a control input of the setpoint channel field polarity "SIN". The output of the EXCLUSIVE OR element is connected to the control input of the COS polarity setpoint generator. 2 Il.

Description

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The invention relates to the control of electric machines and can be used in a discrete electric drive with crushing pitch.

The purpose of the invention is to simplify and increase reliability by reducing the number of elements and connections.

FIG. 1 shows a functional diagram of the device; in fig. 2 - cyclogram of voltages at the outputs corresponding to the elements of the device.

The device contains the same permanent storage devices (ROM) 1 and 2, respectively, of the sin channel and the cos channel, connected by address inputs to the reversible counter 3, and outputs to the corresponding digital-to-analogue transducer bodies 4 and 5 with unit 6 and 7 polarities that are connected with the corresponding controlled stabilizers 8 and 9 of the current, the output AK of the counter 3 connected to the upper address input of ROM 1 and 2 is connected to one of the inputs of the EXCLUSIVE 1 10, and the next most significant bit A (K + 1) of the counter 3 is connected to the second To the input of the EXCLUSIVE OR element and to the control input of the setpoint 6 polar channel sin, the output of the EXCLUSIVE OR 10 element is connected to the control input of the setpoint 7 polarity of the cos channel.

The device works as follows.

In the memory cell of the ROM with addresses 0, ..., N, the sinusoid values of the first two quadrants are written in digital form (Fig. 2), in ROM 2 - the absolute values of the cosine of the first two quadrants in digital form (Fig. 2)

When 3 clock pulses are applied to the counter, digital data, corresponding to the amplitude values, are started from the cells of the ROM from the cell with the address zero to 0.5N. The output analog-to-analog converters 4 and 5 produce analog sine wave and cosine waves of the first quadrant, which are positive with respect to the zero potential and are transmitted by polarity control devices 6 and 7 to the inputs of the corresponding current-controlled stabilizers 8 and 9.

When the counter reaches 3, the state is 0.5N, i.e. setting the address equal to the floor (the fault of the number of recorded

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five

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0

five

0

cells ROM 1 and 2, the state of the AK output of the counter 3 changes.

At the output of the EXCLUSIVE OR 10 element, a signal appears causing the switching of the polarity of the output signal of the polarity setting device 7.

A further change in the states of counter 3 leads to the formation of the second quadrant of the sine wave and the negative value of the second quadrant of the cosinusoid.

When the counter reaches 3, state N, i.e. the maximum address, the ROM changes the output state A (K + 1), the AK output state returns to its original state.

A change in the state of output A (K + 1) and AC leads to the switching of the polarity of the signal at the output of the setpoint generator 6 of the polarity and leaves the work of the setting point 7 of the polarity unchanged. The formation of negative values of the third quadrant of a sine wave and cosine wave occurs. Counter 3 again generates the value of the addresses supplied to ROM 1 and 2 from zero to 0.5N.

When the counter reaches 3, the value of 1.5N changes the state of the AK output, which leads to the appearance of the initial state at the output of the EXCLUSIVE OR element. This signal brings the polarity setpoint 7 to the initial state, i.e. forming a positive cosinusoid value. At the outputs of the setting units 6 and 7 of the polarity, negative values of the sinusoid and positive values of the cosine of the fourth quadrant are formed, respectively.

When the counter reaches 3 N, the formation of the full period of the sine wave and cosine wave ends. Further clock pulses repeat the described process.

The generated sinusoidal and cosine-shaped analog signals are fed to the inputs of the corresponding controlled current stabilizers 8 and 9, which generate current in the phase windings of the stepper motor, varying in accordance with the sinusoidal and cosine-like laws (Fig. 2).

Using the entered element and the links allows to exclude from the prototype circuit an address comparator and

-Tx

Claims (1)

Claim A device for controlling a stepper motor, comprising a reversible counter and sin and cos control channels, the first of which includes a series-connected read-only memory, a digital-to-analog converter with a polarity setter, and a controlled current stabilizer, the address 15 inputs of the read-only memory of each channel being connected to 7 to ⁶ bit outputs of a reversible counter, characterized in that, in order to simplify and increase reliability by reducing the number of elements and connections, an EXCLUSIVE OR element is introduced into it, the reversible counter additionally contains one senior bit, the output of which is connected to the control input of the polarity setter of the channel sin and the first input of an EXCLUSIVE OR element, the second input of which is connected to the second-highest bit output of the reversible counter, and the output to the control input of the channel polarity adjuster cos.