SU1626311A1 - Method of inverter control - Google Patents

Description

The invention relates to electrical engineering and can be used in power supplies for induction installations.

The purpose of the invention is to increase the efficiency of the inverter when operating at varying loads.

Figures 1a, b illustrate examples of inverter circuit diagrams with doubling and without frequency doubling, respectively, in which the control method can be applied; in fig. 2 - functional diagram of the device that implements the method; in fig. 3 shows timing diagrams explaining the nature of the inverter control method,

The inverter of FIG. 1a contains a thyristor bridge on four tons and 2–5 thyristors connected to the input terminals through the filter choke 1 of the filter with a switching terminal 3, a load of 7 and a switching codemptome. : - rum 8 in the diagonal of the variable gok. and t; - the same two successive circuits from the filter capacitor 9, protective throttle 10 and stabilizing thyristor 11 and throttle 12. Resonant-type inverter. The period of the output frequency of the inverter T is determined by the full cycle of the thyristors 2-5 (inverter without frequency doubling).

The inverter of FIG. 1 b contains a linkage with input pins through the path of the filter 13 and a switching throttle ;. Ki thyristor bridge on four thyristors 15-18 with commutation capacitor 19 in alternating current diagonal. Inter / v junction point of chokes 13 and 1- and o; G1 - terminal input terminal included .;

with-.

ivO f g /

- - - l

I jy d

1 g-, -,

A series circuit from load 20, throttle 21 and filter capacitor 22, as well as a stabilizing thyristor 23. Between the anode group of the bridge and the junction point of the throttle 21 and capacitor 22 a series circuit is connected from the capacitor 24 and the cut-off diode 25, the junction point of which is connected to negative input terminal through an additional choke 26. The presence of the specified circuit provides the rigidity of the external characteristics when the load resistance decreases in the direction of, For a cycle of operation of all thyristors 15-18 in the load of 20 half Two full output voltage periods (frequency doubling inverter) are given.

A device for implementing the method (Fig. 2) contains a controlled master oscillator 27, a pulse distributor 28 connected to the output of the master oscillator and the inputs of the pulse shapers 29 and 30, the outputs of which are connected to the inputs of the output stages 31 and 32 connected to the inverter 33, sensors 34 is a voltage on a switching capacitor and a thyristor current sensor 35, the outputs of which are connected to the inputs of summing element 36. The output of element 36 is connected to the input of comparator unit 37, to the second input of which a setpoint signal is received from source 38 ask. The output of block 37 is connected to the control inputs of the master oscillator 27, the key element 39, and the block 40 of an adjustable delay. The input element 39 is connected to the output of the master oscillator 27, and the output with the input of the block 40, the output of which is connected to the input of the driver 41 pulses. The output of the driver 41 is connected to the input of the output stage 42, the output of which is connected to the control electrode of the stabilizing thyristor in the inverter.

The inverter control method is implemented as follows.

Assume that the inverter (Fig. 1a) works without a pause, i.e. Immediately after the oscillating current of the switching circuit of the inverter, including chokes 6 and 10, load 7 and capacitors 0 and 9, and turning off the thyristors of one of the bridge diagonals (for example, 2 and 5), the thyristors (for example, 3 and 4) of the second diagonal are turned off. The current through the load 7 and the switching capacitor 8 has the form shown in FIG. 36. The position of the thyristor control pulses of the bridge is shown in FIG. Behind. With each current pulse, the commutating capacitor 8 is recharged and the voltage form on it has the form shown in Fig. 3c.

In this case, the voltage on the switching capacitor 8 changes sign through a 0.25 T period of the inverter output frequency after each unlocking of the thyristors 2.5 or 3.4

bridge diagonals. If the inverter is operating at rated load, then the voltage across the cells and the losses are minimal. Inverter has maximum efficiency

Load resistance change,

0 for example, in the direction of decreasing leads to an increase in the quality factor of the switching circuit, the buildup of voltage on the JUP-elements and currents through them, as well as an increase in losses. When turning on lg thyristor 11, a closed loop of circulating recharge of the switching com- trade tr-e 8 is formed - a circuit including thyristors l S. 1 1, throttles 6, 12 and load 7 or thyristor

0 3, 4, 11, chokes 6 and 12 and load 7 not containing a power source. A test of this circuit increases the input resistance of the inverter when the load changes and provides the required rigidity of the external characteristic. At the same time, the change in the resistance of the load: - ki n} iodite to a decrease in the sweat r, -l and the energy from the power source 1, the losses in the elements increase on the second.

0 knowledge

The stiffness of the external characteristic depends on the coefficients (.g of the inductance in the inversion circuit of 0p K LG / (MO + Le) and the value of the inductance of the throttles 12

5 Li2. In this case, Li2 should be chosen sufficiently small to ensure that the reverse voltage on the off thyristors is within 20-30 P (the most optimal level of reverse magnetization on the thyristors is in the range of controlling the control properties). Phgtic I. does not affect the processes in the switching circuit. Reducing K provides greater rigidity of the external ASG

5 performance and higher 1 efficiency phi operation of the inverter for a load different from the nominal. However, in the etsi case in the nominal mode, through sta6il - the irreducible thyristor proceeds

0 circulating current, reducing you / one of the power and increasing the total losses and elements. The efficiency of the inverter is low. In this method, in the nominal mode, the stabilizing thyristor is not

5 include (control pulses are not applied to it).

Coefficient K is selected from the requirements of obtaining the greatest hardness of the external characteristics of the inverter when working on a variable HC load, 3

permitted range of currents and voltages in which control pulses are not supplied to the stabilizing thyristor When operating in the permitted range, minimum losses in the elements are maintained by adjusting the frequency as a function of the measured currents of the bridge thyristors and the voltage on the switching capacitor 8 This also ensures the external characteristic stiffness.

With the increase of the specified parameters, the frequency of supplying the control pulses is reduced to the minimum value. After reaching the limit values as a function of the indicated currents and voltages, the phase shift r starts to decrease between the moments of supply of control pulses to thyristors 2-5 and the moment of supply of control pulses to stabilizing thyristor 11 from 0, 25 G to 0 (in the most non-Slaughter mode with a nozzle as maximally different from the nominal one) The change is illustrated by the diagrams in Fig. 3 g, f, g, where the position of the pulses is shown. effects of stabilizing thyristor 11 and circulating current through it

If the control pulse arriving at the thyristor 11 is shifted by zo by an angle τ close to 0.25 T, then the switching capacitor 8 is practically perrissive (Fig Zv, d, e), therefore, the stabilizing thyristor 11 is switched on for a short time and causes a slight cir. street and current. The effect on the processes in the circulating current inverter is insignificant and the losses from it are insignificant. However, the strength of the external characteristic of the peak value is

A further decrease in t leads to an increase in the duration of the conductive state of the thyristor 11 and the amplitude of the current through it (Fig. 3c, g), the input resistance of the inverter increases, and the power consumption from the power supply and the losses in the inverter elements decrease. At the same time, the circulating current depends on the mode always the minimum possible, which ensures low losses in the elements and high efficiency of the inverter. The measured current and voltage are the most representative parameters, the control of which allows optimal control of the ratio of output power to power loss.

The device for implementing the method operates as follows

The controlled master oscillator 27 generates pulses with a period T, which are fed through the distributor 28 to the formers 29 and 30 and through the weekend

cascades 31 and 32, amplifying pulses up to the required amplitude, on thyristors of diagonals of inverter bridge 33. Shapes 29 of IZO serve to generate pulses 5 of required duration, ensuring economical and reliable switching on of thyristors of inverter 33 If the voltage on the switching capacitor and the current of the thyristors of the inverter 33 are lower than the lower ones limit levels, which corresponds to the nominal mode of operation of the inverter, the element 39 disables the output of the master oscillator 27 from the input of the block 40. In this case, the supply of control pulses is prohibited

5 to the stabilizing thyristor G by increasing the voltage on the switching capacitor or the current of the thyristors of the inverter bridge 33, when the mode of operation of the inverter does not correspond to the nominal, which is caused, for example, by changing the load resistance from a variable value for the inverter 33, the signals at the outputs of the sensors 34 and 35, therefore, at the output of epimete 36 and block 37

5 If, at the same time, the voltage on the switching capacitor and the current of the thyristors and the upper limit of the power supply, the element 3 is in the initial state and the output of the generator 27 is disconnected from the input of the block 40

0 Control pulses to the stabilizing thyristor are not received. Regenerate 4 m1 of measured voltages and the go-mt of the master oscillator 27 according to the error signal between the voltage from the output of the element 36 and the voltage from the I-source of the source 38 and from the output of the unit 37 At the same time, with an increase in the current and voltage of the generator generator 27, you decrease 1 and vice versa.

If the voltage of us is exceeded by the commutator capacitor or the thyristor current of the upper limit levels, which corresponds to a higher signal level at the output of the block 37, the ephemont 39 connects the output of the generator 27 to the input о / у-а

5 40. The pulses of the generator 27 through the block 40, the driver 41 and the output stage 2 arrive on the stabilizing days of the thyristor. Next, the function of the measured current and voltage of the phase shift angle r between the unlocking of the thyristors of the bridge and the stabilizing thyristor according to the signal from the output of block 37 is regulated. The signal level at the output of block 37, corresponding to the moment of accumulation of the element 39, ensures the pulse delay of the generator 27 by block 40 by 0.25 T. A further increase in the signal at the output of block 37 with an increase in the voltage on the switching capacitor or the current of the bridge thyristors leads to a decrease in the phase shift t in the range from 0.251 d oo.

When using the described method, the efficiency of the inverter when operating at varying loads is increased by 5-7%. In all possible modes of operation, the OTL.VTC is minimized.

CURRENT, PROP: 1J CIC CHOZE SL ABILIZING

thyristor As a result, the optimal ratio of output power is sacrificed — the power of losses with the required rigidity of the upper characteristic. At the same time, the rigidity of the external characteristic can be increased, since the distribution coefficient K of the inductance K in the circuit can have a smaller value while maintaining the output power and efficiency at the highest (pozmokhnom) level in nominal mode

Claims (1)

Increase also the reliability of the inverter and. The capacity of the power ooo / dl is not at the expense of a more rigid VIRIAH / akgergistiki in the range of parameters of the load parameters and the implementation of the inverter but the specified power. The Invention Method An exercise invertorg, containing a bridge bridge with a coherent capacitor and a stabilizing thyristor, in particular, TO form control pulses and feed them to the thyristors of the bridge diagonals with a phase shift of half the period T output frequency of the inverter and the stabilizing thyristor with a phase shift relative to the moments of the supply of control pulses to the bridge thyristors, characterized in that, in order to increase the efficiency of the inverter, the lower and upper limit levels of the voltage on the switching capacitor and the current of the bridge thyristors are measured the switching capacitor and the current of the thyristors of the bridge, compare the measured values with the given limit levels, if the measured voltage and current are less than the lower limit levels, prohibit the impulse The settings for the stabilizing thyristor, if the measured values are higher than the lower and lower upper limits, regulate, as a function of the measured voltage and current, the frequency of the supply of bridge thyristor control pulses, and with increasing current and voltage, the frequency is reduced and vice versa, if the measured voltage or current is higher the upper limit levels, fix the frequency of the supply of control pulses to the thyristors of the bridge at the reached level, allow the supply of control pulses to the stabilizing thyristor, regulate as a function GOVERNMENTAL current and voltage value of the phase shift d in the range 0.25 T m, and with increasing voltage or current value of m is decreased. but o-- 49ig .1