SU1638781A1 - Inverter - Google Patents

Abstract

The invention relates to a converter technique and can be used as a power source for electrical technology and ultrasonic installations. The goal is to improve the harmonic composition of the output current. The device contains connected to the input terminals via chokes 1.2, a bridge on ty2Tristores (T) 3-Ь and a series circuit from the capacitor 8, load 9 and throttle 10. The control unit 14 is connected to the output of the frequency divider 19, the input connected to a master oscillator 15. The capacitor 8 voltage sensor 16 is connected in series with a comparison device 17, an adjustable delay unit 21, an HE element 22, a fixed delay unit 23, a first driver 24 pulses and an output stage 25 To the control electrode T 11. The control electrode T 12 is connected to the second output. cascade 27 connected via a second pulse shaper 26 to RHD 21. Frequency divider 19 is connected via element 20 to BRZ 21. By setting the interval between the unlocking of the thyristors using a fixed-delay unit 23, the first harmonic level in the output current is increased. 2 Il. 10 OS oE 00 00 Phage /

Description

The invention relates to a converter technique and can be used as a power source for electrical technology and ultrasonic installations.

The purpose of the invention is to improve the harmonic composition of the output current.

On fn.1 shows a diagram of the inverter; figure 2 - timing diagrams at the outputs of the elements.

The inverter contains a thyristor bridge on four thyristors 3-6 with a switching capacitor 7 in the AC diagonal and a series circuit from the first capacitor 8 of the filter, the load 9 and switching throttle 10, the first valve connected to the input terminals via the first 1 and second 2 filter chokes. (thyristor) 11, connected by the anode with the point of connection of the load and the switching throttle, and the cathode - with a positive input terminal, the second valve (thyristor) 12, connected by the anode with the outlet of the switching throttle, and the cathode - with ano A second group of filter capacitor 13, connected between a positive input terminal and a cathode group of a thyristor bridge, a control unit 14 with a master oscillator 15, the outputs of which are connected to the control electrodes of the bridge thyristors, a voltage sensor 16 on the first filter capacitor, comparison device 17, reference voltage source 18, series circuit of frequency divider 19, AND element 20, adjustable delay unit 21, HE element 22, fixed delay unit 23, first impedance driver 24 and the first output stage 25, a series circuit of the second pulse generator 26 and the second output stage 27, the voltage sensor output being connected to the first input of the comparator, the second input of which is connected to the output of the reference voltage source, and an adjustable delay unit, the input of the frequency divider is connected to the output of the master oscillator, the output is connected to the input of the control unit. and the other output is connected to the first input of the element I, the second input of which is connected to the output of the master oscillator, the input of the second imprinter is connected to the output of the control unit

0 about 5 about,.

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of the delay time, the first output stage is connected to the control electrode of the first valve, and the second output stage to the control electrode of the second valve.

Inverter in the steady mode works as follows.

The control unit 14 generates thyristor control pulses 3-6 of the inverter bridge at intervals of T 1 /, where f is the output frequency of the inverter (1, figure 2). The pulses are fed to the thyristors of the diagonal of 3.6 or 4.5 bridges. When the thyristors are unlocked by any diagonal of the inverter bridge, for example, 3.6, an oscillatory overcharge of the switching capacitor 7 begins along the circuit 7-6-10-9-8-3-7. If the sum of the voltages on the first capacitor 8 of the filter, the load 9 and part of the commutating throttle 10 becomes positive for the second valve 12, then conditions for its inclusion appear. The second valve 12 turns on if a control pulse is applied to it from the output stage 27. When the second The valve 12 forms a new additional circuit for recharging the switching capacitor 7 through the circuit 7-6-10-12-3-7. This circuit is separated from the power source, and when it occurs, the power consumption of the inverter from the source is reduced. The load characteristic of the inverter becomes more rigid. After the voltage at the second valve 12 becomes negative, it turns off. The positive voltage on the valve 12 is maintained at a time interval of about T / 4 from the moment the thyristors of the bridge diagonal are turned on until the capacitor 7 is recharged (its polarity is shown in Fig. 1). By varying the time t / j of switching on the valve 12 with respect to the beginning of the period in the interval O-T / 4, the duration of the conductive state interval and the effectiveness of the influence of the additional recharge circuit of the switching capacitor 7 on the stiffness of the inverter characteristic can be adjusted. After the valve 12 is turned off, the recharge current of the capacitor 7 continues to flow along the initial circuit. When the oscillating-current recharging of the capacitor 7 reaches its maximum value, the polarity of the voltage across the switching choke 10 changes. As the current decreases, this voltage increases. As soon as it exceeds the voltage on the second capacitor of the filter 13, conditions arise for switching on the first valve 11. The valve 11 is turned on if an output stage control pulse 25 is applied to it. After the valve 11 is unlocked, the current of the thyristors 3 and 6 of the bridge decreases rapidly and they are turned off. Current throttle 10 continues to flow through the valve 11 through the chain 10-11-13-10. This circuit exists until the electromagnetic energy stored in the throttle field 10 is consumed. When the valve 11 is operating, energy is returned from the inverter switching circuit to the power source, as a result of which the inverter load characteristic becomes more rigid. The conditions for switching on the valve 11 exist depending on the load resistance in the interval T / 4-T / 2. Change moment t ,. switching on valves 11 with respect to the beginning of the period, it is possible to adjust the duration of the interval of its conducting state, the amount of energy returned to the power source, and the rigidity of the load characteristic. The current through load 9 changes direction. After switching off the valve 11, the current through the load 9 is provided by pumping the filter capacitor 8 through the chokes 1 and 2 Lilters from the power source. There is a pause in the operation of the inverter, which is necessary to improve the harmonic composition of the load current, a pause that lasts until the thyristors 4 and 5 are switched on. After the thyristors 4 and 5 are turned on, the processes in the interval are repeated. Figure 2 shows the timing diagram of currents I of the bridge diagonals corresponding to the nominal mode of operation (the load resistance is equal to the nominal value) when the gates 1 and 2 are unlocked at times Y and T / 2, respectively.

This mode refers to the case where the error signal at the output of the comparison device 17 between the voltage on the first filter capacitor 8 measured by the voltage sensor 16 and the output voltage of the reference voltage source 18 is minimal. When the resistance changes; load 9, both in the direction of decreasing and increasing, the voltage on the first filter capacitor 8 and the error signal at the output of the comparison device 17 increase. Block 21 adjustable delay shifts control pulses

valves 11 and 12 in the direction of decreasing ft and U1, resulting in stabilized operation. Inverter rudder characteristic is tough. In this case, return unnecessary

5 energy from the switching circuit is adjustable and depends on the mode of operation of the inverter. Figure 2 shows the current pulses I, $ at the output of the master oscillator 15. Their frequency is equal to

0 4f. These pulses are fed to a frequency divider 19, having outputs with division factors of two (2f) and four (f). Pulses TC), 119 at the outputs of the divider 19 are depicted, respectively, in FIG. Pulses with a frequency of T 1 / f are sent to control unit 14. Of these, the latter forms the control pulses Iu of the thyristors of 3–6 bridges (FIG. 2). Impulses

0 of the master oscillator 15 and the divider 19 frequencies with a frequency of 2f are fed to the element And 20. At the output of the element And 20 are formed reference

PULSES 12o (FIG. 2) AHHTej; By the night

5 T / 4. These pulses arrive at the input of the variable delay unit 21, where they are shifted by an angle of / 3 (Fig. 2) in accordance with the output signal of the comparison device 17. Next impulse sy I 2, from the output of block 21 is fed to the driver 26 pulses (signal to the output ° Deformer 26)

and through the output stage 27 of the control electrode of the second valve 12.

5 The pulses of block 21 are also fed to the input of the element HE 22 (signal. At the output of the element HE 22). The signal from the output of the element NOT 22 is fed to the input of the block 23 of a fixed delay; At the output of this block, the reference pulses are shifted by the cell J T / 4 (T2c of figure 2). The shaper 24 pulses from the reference pulses from the output of the block 23 generates pulses 154

5 (FIG. 2), which through the output stage 25 are fed to the control electrode of the first valve 11. The diagrams in FIG. 2 correspond to some intermediate signal from the output

the comparison device 17 between the minimum and maximum signals. The fixed delay unit 23 is designed for a fixed offset by a certain angle, larger and / 4, of the control pulses of the second 12 and first 11 valves (Y - | i 1t / 4), which is set during the tuning steps and ensures reliable unlocking of the valves.

A purely alternating current flows through the load, since the constant component does not let the filter capacitor pass, and the return of excess electromagnetic energy is carried out along a circuit that does not contain a load. In addition, the energy is returned from the inverter switching circuit both with the increase (fan 12) and decay (valve 11) of the current of the bridge thyristors. Setting the interval between the valve unlocking times using a fixed-delay unit 23 ensures a further increase in the first harmonic level in the inverter output current. Making the controllable valve 11 allows for the return of excess electromagnetic energy from the switching circuit only when the load 9i changes. In this case, the energy return is adjustable, which generally improves efficiency.

Claims (1)

Invention Formula Inverter containing thyristor MOS connected to the input terminals through the first and second filter chokes with a switching capacitor in the diagonal of alternating current and a series circuit from the first filter capacitor, output terminals and the switching droplet, the first cathode of which is connected to the positive input terminal, second valve, anode which is connected to the outlet of the commutating choke, and the cathode - with ANODOUS GROUP OF THYRISTOR BRIDGE, the second filter capacitor, connected by the first plate to the positive input terminal, and the second to the cathode group of the thyristor bridge, the control unit, whose outputs are connected to the control electrodes of the bridge thyristors, which drive the generator, in order to reduce the size by improving the harmonic composition of the output current, it is equipped with a voltage sensor on the first filter capacitor, a comparison device, a reference voltage source, a frequency divider having an input and two outputs with dividing two and four, respectively, by the first serial circuit from the AND element, the adjustable delay unit with the control input, the NOT element, the fixed delay unit, the first pulse generator and the first output stage, the second serial circuit from the second pulse driver, and the second output stage the valve is connected to the connection point of the switching throttle with the output terminal, and the valves are controlled, the output of the voltage sensor is connected to the first input of the comparison device the second input of which is connected to the output of the reference voltage source, and the output to the control input of an adjustable delay unit, the input of the frequency divider is connected to the output of the master oscillator, and the output with a division factor four - with the input of the control unit, the output with a division factor two - with the first input element And, the second input of which is connected to the output of the master oscillator, the input of the second pulse shaper is connected to the output of the adjustable delay unit, the first output stage is connected to the control electrode of the first entil and the second output stage - to the control electrode of the second gate.  U b ivs .7 hh: And w | five  / / .. h J19b P P P P P P P And w | five g7