SU1485400A1 - Analog-to-digital converter - Google Patents

Description

The invention relates to electrical Invention relates to electrical measuring and computing equipment and is intended for encoding fast-changing electrical signals into a digital code.

The aim of the invention is to increase speed.

FIG. 1 is a block diagram of the device; in fig. 2 - analog-to-digital conversion unit.

The device contains the first summing amplifier 1, whose input is connected to the input of the device, analog-digital converter 2, delay element 3, digital-to-analog converter converter 4, register 5, second summing amplifier 6, analog-digital conversion unit 7, digital adder 8, first 9 and second 10 form2

measuring and computing technology and is designed to encode rapidly changing electrical signals. The aim of the invention is to improve performance. The goal is achieved by introducing a pulse generator, a trigger, a second summing amplifier, a delay element, a registrar, and drivers into a device containing an analog-digital converter and an analog-digital converter unit, a digital-analog converter, a summing amplifier and a digital adder. The device allows for the expense of reducing the transition time in the sum of the amplifier to reduce the conversion time. 1 hp f-ly, 2 ill. ·

world leaders, trigger 11, generator 12 pulses.

Block 7 analog-to-digital conversion consists of analog-to-digital Converter '13 and shaper 14.

The device works as follows.

The generator of 12 pulses continuously generates start signals on the analog-to-digital converter 2 with often '5 „1

one equal to £ =, where

^t pr ADC

T _P p d _P ^- conversion time of analog-to-digital converter 2.

The code from the outputs of analog-to-digital Converter 2 is fed to the inputs of the digital-to-analog converter 4,

5Ts „1485400 A

3

1485400

four

is converted into an analog signal, which is fed to the first input of the first summing amplifier 1, to the second input of which an analog signal is fed from the output of the element 3 for the * delay. The latter provides a delay of the input signal at the time

^{= t} pr, ADC ^{+ t} pr. ήυ, η ” ^{where τ} ηρ. Αϋ, Π the conversion time of the digital-to-analogue converter 10 of the converter 4. Summing amplifier 6 serves to match the input of the device, as well as to bias the input signal by the value of the II _CAA to ensure the coding of the bipolar 15 signal. Upon receipt of the pulse "Run" shaper 9 generates a pulse of duration not less than

T _p p _A p _n . The front of this pulse switches the trigger 11 and turns off the 20 generator of 12 pulses. The falling edge of this pulse code from the outputs of analog-to-digital converter 2 is recorded in register 5. From the output of driver 10, a trigger pulse delayed relative to the pulse from driver's output 9 is sent to the trigger input 25 of analog-digital conversion unit 7 , _{A. CPU} + T _{pr Atsp} . The analog-to-digital converter 13 (Fig. 2) of block 7 encodes the voltage from the output of summing amplifier 1, which represents the amplified difference between the input signal and the voltage from the output of the digital analog converter 4. The result of the conversion is summed up by the digital adder 8 with the result of the first conversion and enters the output device. A 40-unit analog-to-digital conversion block 7 'shaper 14 (FIG. 2) provides a delay of a triggering pulse arriving at its input for a time equal to T _P p _{A (} ^ _n . This pulse 45 from the output of shaper 14 (Fig. 2 a) trigger 11 is switched, including the generator of 12 pulses before the arrival of the next “Start” pulse.

50

Thus, due to the constant launch of analog-digital converter 2 and providing the input signal tracking mode, the overload of summing amplifier 1 is minimal and, accordingly, the transient process time is reduced, which allows reducing the conversion time of the entire device and thereby increasing its speed.

Claims (2)

Claim 1. Device for analog-to-digital conversion containing analog-to-digital Converter, the outputs of which are connected to the corresponding inputs of the digital-to-analog converter, the output of which is connected to the first input of the first summing amplifier, the output of the first summing amplifier is connected to the first input of the analog-digital conversion unit, the first outputs which is connected to the corresponding inputs of the digital adder, the output of which is the output bus, characterized in that, in order to increase speed , a second summing amplifier, a pulse generator, a trigger, a delay element, a register, first and second drivers, the input of the first of which is a “Start” bus, are entered into it, the output is connected to the input of the second driver, the first trigger input and the first register input, output The second driver is connected to the second input of the analog-digital conversion unit, the second trigger input is connected to the second input of the analog-digital conversion unit, the output is connected to the input of the pulse generator, the output of which is connected to the th input of the analog-digital converter, whose second input is connected with the output of the second summing amplifier and combined with the input of the delay element, the first and second inputs of the second summing amplifier are connected respectively to the first and second input buses, the output of the delay element is connected to the second input of the first summing amplifier, the output of the analog-digital converter is connected to the second input of the register, the output of which is connected to the second input of the digital adder. 2. Device by π. 1, characterized in that the analog-to-digital conversion unit is performed on an analog-to-digital converter and a driver, with the first input of the unit being information analog-to-digital input1 ⁵ 1485400 ° For, the second input of which is combined by the block, are the outputs of the analog-to-digital input of the driver and is a smooth converter, and the second is 2