SU1483492A1 - Memory - Google Patents

Abstract

The invention relates to computing and can be used to build display RAM storage devices with a short access time when recording information intended for accumulating buffer storage of an image bit map synthesized by a computer or a graphics processor and regenerating an image on a television monitor screen. The purpose of the invention is to increase the speed of the device. The device contains a register 1, the first switch 2, N single-bit storage 3 ₁ -3 _N dynamic type, the decoder 4, the second switch 5, N elements And 6 ₁ - 6 _N. Improved performance in block writing is achieved through the use of paging in single-bit drives. 1 il.

Description

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The invention relates to computing and can be used in the construction of storage of a display random access memory device with a short access time for recording information and intended for accumulation, buffer storage of an EVA or graphic processor synthesized by an EHR or image processor. on the screen of the television monitor,

The purpose of the invention is to increase speed by reducing the average access time when recording a generated bitmap of a graphic image in a display memory.

Ia drawing schematically shows the proposed storage device.

The device contains a register 1, the first switch 2, N single-bit drives 3 of the dynamic type, the decoder 4, the second switch 5, N elements II b. The drawing also indicates: the first 7 and second 8 device access inputs, address connection control input 9, the first mode setting input 10, the third mode setting input 11, the mode setting inputs 12, the second mode setting input 13, the information input device 14, informational 15 device outputs, addressable device 16 inputs. The device contains m address inputs A1 ,. ".,

AK AMI A p; / (+),. . , Lmi, L (the addressable space of a bitmap of a graphic image is 2 tons), while only a part or weight of the specified space of a graphic image can be displayed depending on the frame format and resolution of the raster monitor. The youngest group of addresses A,. . ,, L c provides access to a separate one-bit drive 3. The remaining bits of the address A K4,,. .., At address the indicated words in the rectangular coordinates X, Y of the image bitmap: address group A1,. .., A {corresponds to the X coordinate, a A ff ,,. . . Am is the Y coordinate, and the bitmap of the image is calculated by the GPU or computer element by element in the specified rectangular coordinates. One-to-one correspondence between sets of address spaces

The proposed device and the group of one-bit drives of the dynamic type are set as follows: the group of address inputs of the RAS line (in ascending order) corresponds to the address inputs of A to,,. . . , Ar; At the group of address inputs of the column CAS correspond A,,. . . , A t,, and k + 1, ..., 1 bits of the address inputs of the device are involved in information regeneration.

The device works as follows.

Read mode In the mode of reading information on the display, a call is made simultaneously to all one-bit storage drives 3, and the address of the word to be displayed is fed to the group of address inputs 16 of the device A fc + 1,. . . 5 A „,. At the device input 9, the first switch 2 connects the information inputs of the second group to the corresponding address inputs of the drives 3. The address is received to the drives 3 by the line address strobe signal received at the second control input 8 of the device. Then, at the device input 9, the first switch 2 connects the information inputs of the first group to the corresponding address inputs of the specified drives 3, and the address is received to the drives 3 by the address strobe signal

column coming to the first input 7 of the device. The readout of the data word for display is carried out from the information outputs 15 of the device. In the read mode, the write enable signal is not given to input 10 of the device mode setting (inactive state). In the read mode, the mapping is performed by sequential enumeration of addresses by groups / k +,,. . . , Af; A {+,,. . . Am, while the regeneration of the drives is performed during the issuance of one line of the image raster.

Recording mode Block record.

From the prepared bitmap array of the image, the data in the form of words (blocks) is fed to the inputs 12 of the device mode and the signal at the second control input 13 of the device is written to the register 1, from the output of which data is fed to the information inputs of the second group of the second switch 5 and signal from

the control input 11 of the device is fed to the second inputs of the corresponding elements AND 6, which is the mask of the recording resolution signal received at the input 10 of setting the device mode. The value of the recorded data (0 or 1), i.e. changing the content of the image bitmap, opFormula 5 rete nn and the memory device containing the register, the first switchboard, N one-bit dynamic type storage devices, the same name inputs of the column address gates and the rows of which are combined and are respectively the first and second access inputs of the device

determined by the state of the informational | 0 device, the address inputs of the drives of the device input 14. The boost is produced and connected to the output via a block recording of the secondary switch, the control input is caused by the use of which is the first input of the page record single way in which the address of the device is connected. The address access to the 15, the first, and the second, drive 3 is carried out similarly to the read mode, while fixing the address of the RAS row of the one-bit drives 3 in the first write cycle, and in subsequent cycles writing to the write inputs the readings of the corresponding information are performed only through the search of accumulative addresses, the outputs of which are groups of the address of the CAS column of the accumulative information outputs of the device, lei 3 (with the same row address), the information inputs of the accumulators and the second control input 8 are merged and ormatsionnym roystva is in the active state -25 input device, first inputs of all

that, for the purpose of a new speed target of the device, a descrambler is inserted into it, the second set of N elements H, whose outputs are connected to

and the first switch 2 on the control input 9 of the device connects groups of address inputs 16, ..., Am, devices to the corresponding address inputs of drives 3,

Item record. The address of the element in rectangular coordinates X, Y is given to the group of address inputs 16 of the device A, ..., At, whereby the selected word is accessed in the same way as the read and block write modes, and the specific element of the selected word is accessed by minor bits

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And elements are combined and are the first input of the device mode setting, the outputs of the second switch are connected to the second inputs of the corresponding AND elements, the information inputs of the first group of the second switch are connected to the register outputs, the information inputs of which are the device mode setting group input The second input of the device mode setting, the decoder inputs are the address inputs of the first device group, the decoder outputs

/,,..., BUT

frame inputs 16 devices. The specified address is fed to the inputs of the decoder 4 and then the position code of the selected element on the control input 11 of the device by the second switch 5 is fed to the second inputs of the And 6 elements in the form of a mask for the write enable signal supplied to the input 10 of the device's mode setting.

The drives, the drive's input inputs are combined and connected to the output of the first switch, the control input of which is the first input connected to the address of the device, which is connected to the write-read inputs of the corresponding memory. The outputs of which are the information outputs of the device, the information inputs of the drives are combined and are the information input of the device, the first inputs of all

that, for the purpose of a new speed target of the device, a descrambler is inserted into it, the second set of N elements H, whose outputs are connected to

five

And elements are combined and are the first input of the device mode setting, the outputs of the second switch are connected to the second inputs of the corresponding AND elements, the information inputs of the first group of the second switch are connected to the register outputs, the information inputs of which are the device mode setting group input The second input of the device mode setting, the decoder inputs are the address inputs of the first device group, the decoder outputs

Q is connected to the information inputs of the second group of the second switch, the control input of which is the third input of the device mode setting, the information inputs of the first

The 5 groupings of the first switch are the address inputs of the second device group, the information inputs of the second group of the first switch are the address inputs of the third group of the device.

Claims (1)

The formula of 5 retention: A storage device containing a register, a first switch, N dynamic-type single-bit drives, the inputs of the same name address strobes of the column of the first row are combined and are respectively the first and second inputs of the device access, the address inputs of the drives are combined and connected to the output of the first switch, the control input of which is the first input to control the device address connection we have a decoder, a second switch, and N AND elements, the outputs of which are connected to the write-read inputs of the corresponding drives, the outputs of which are the information outputs of the device, the information inputs of the drives are combined and are the information input of the device, the first inputs of all AND elements are combined and are the first input of the mode devices, the outputs of the second switch are connected to the second inputs of the corresponding elements And, the information inputs of the first group of the second switch are connected to the outputs of the reg device whose information inputs are the inputs of the device mode setting group, the register synchronization input is the second input of the device mode setting, the decoder inputs are the address inputs of the first device group, the decoder outputs are connected to the information inputs of the second group of the second switch, the control input of which is the third mode setting input devices, information inputs of the first group of the first switch are address inputs of the second group of the device, information inputs of the WTO The swarm groups of the first switch are the address inputs of the third device group.