SU1481748A1 - Multiplier - Google Patents

Abstract

The invention relates to computing and can be applied to quickly perform the operation of multiplying binary and decimal numbers. Its use is especially effective when applying LSI and VLSI. The aim of the invention is to reduce hardware costs due to the new organization of communications. The device for multiplying numbers contains a group of 1 multiplication blocks, a group of 2, 3 summation, a group of buffer registers 5-7 and a group of registers 8 product. 2 hp ff, 5 ill.

Description

29

22 23

J

28

A / g

18r

16р

31

Er

thirty

.19 20

2

, U20

Y20

F t + s

Y20

t + 4

U23

t + 5

Y 20, Y 23

FIG.

UG9, U2v, U 22

Y 20, Y 22

J, / n + 3

Y 20, Y 22

t + 4

22

t + 5

U20, U22, U23

Claims (4)

Claim 1. A device for multiplying numbers, containing a group of multiplication blocks, two groups of summation blocks, a group of product registers and three groups of buffer registers, the input of the multiplier of the device connected to the inputs of the multiplier of the multiplication blocks of the group, the inputs of the multiplicable connected to the corresponding inputs of the digits of the multiplicable group of the device, the input of the job of the mode of which is connected to the inputs of the job of the mode of blocks of multiplication of the group, with the inputs of the job of the mode of blocks of summation of the first and second groups, the outputs of the senior and minor parts the buildings of the multiplication blocks of the group are connected to the information inputs of the corresponding buffer registers of the first and second groups, the outputs of the buffer registers of the first group are connected to the first information inputs of the corresponding summation blocks of the second group, the output is P (P = 1 — Μ, M = n / 4, n - bit depths) of the buffer register of the second group is connected to the second information input of the (P + 1) -th summing unit of the second group, the outputs of the summing units of the second group are connected to the information inputs of the corresponding buffer Istrov of the third group, the installation inputs to “0” of which are connected to the input of the initial installation of the device, the outputs of the sum of the summation blocks of the first group are connected to the information inputs of the corresponding product registers of the group, the output of the Pth register of the product of the group is connected to the first information input (P + 1) of the 1st block of summation of the first group and is the output of the Pth digit of the older part of the product of the device, the output of the younger part of the product of which is connected to the output of the (L4 + 1) -th register of the product of the group, the input of the initial The device configurations are connected to the installation inputs at “0” of the product registers of the group, the reception permission inputs of which are combined with the reception permission inputs of the buffer registers of the first, second and third groups and connected to the first clock input of the device, characterized in that, in order to reduce hardware costs, the inputs of the first and second constants of the device are respectively connected to the second information input of the first and £ first information inputs of the (L4 + 1) -th summing units of the second group, the input of the correction value of the device is connected inen with the first information input of the first summing unit of the first group, the outputs of the buffer registers of the third group are connected to the second information inputs of the corresponding summing units of the first group, the reset inputs of which are combined with the reset inputs of the summing units of the second group and are connected to the input of the initial installation of the device, the first and second clock the inputs of which are connected respectively to the first and second clock inputs of the summation blocks of the first group, the clock inputs of the summation blocks of the second group s connected to the first clock input of the device, the transfer input. The nth summation block of the first group is connected to the transfer output of the (RN) th summation block of the first group, the transfer input of the (D4- | -1) th summation block of the first group is connected to the logic zero input of the device. 2. The device according to π. 1, characterized in that the summing unit of the first group contains an adder, 'corrector, trigger and multiplexer, moreover, the output of the sum of the adder is connected to the information input of the corrector, the inhibit input of which is connected to the transfer output of the adder and with the trigger information input 1, the corrector output and the transfer output of the adder are respectively the output of the sum and the transfer output of the summing unit of the first group, the mode reference input, the first and second clock inputs and the reset input of which are connected respectively to the mode reference input the corrector, the trigger enable permission input, the multiplexer control input and the trigger input to the trigger “0”, the first informational 2 input of the summing unit of the first group is connected to the input of the first summand _; a matora, the inputs of the bits of the second term of which are connected respectively with the inputs of the bits, except for the lowest, second information input of the summing unit of the first group and with the trigger output, the input of the least significant bit of the second information input and the transfer input of the summing unit of the first group are connected respectively to the first and second information inputs multiplexer, the output of which is connected to the transfer input of the adder. 3. The device according to π. 1, characterized in that the summing unit of the second group contains an adder, corrector and trigger, 5 wherein the first and second information inputs, a reset input, a clock input and a mode input of a mode setting of the summing unit of the second group are connected respectively to the inputs of the first and second components of the adder, the installation input "0" and the trigger enable input, with the input of the corrector mode setting, the output of which is the output of the summing unit of the second group, the total output of the adder is connected to the information input of the corrector, the permission input which is connected to the transfer output of the adder and with the information input of the trigger, the output of which is connected to the transfer input of the adder. FIG. 4 I fi 2.5 Compiled by A. Klyuyev Editor L. Gratillo Order 2690/49 Tehred I. Veres Corrector A. Obruchar Circulation 669 Subscription VNIIIPI State Committee for Inventions and Discoveries under the State Committee for Science and Technology of the USSR 113035, Moscow, Zh-35, Raushskaya nab., D. 4/5 Production and Publishing Plant "Patent", Uzhhorod, st. Gagarina, 101