SU1480121A1 - Fibonacci p-code pulse counter - Google Patents

Abstract

The invention relates to computing, information-measuring technology and automation and can be used for counting pulses with the representation of their number in p-Fibonacci codes. The goal is to ensure control of the accuracy of the account. The counter contains OR elements, counting triggers, AND elements, triggers, D-trigger, NOT element, delay element. An increase in the confidence of the counting is achieved by implementing a convolution operation with recording information in a D-flip-flop, the output of which allows monitoring the presence of a failure. 2 tab., 4 Il.

Description

The invention relates to computing, information-measuring technology and automation and can be used for counting pulses with the representation of their number in p-Fibonacci codes.

The purpose of the invention is to ensure control of the authenticity of the account.

ha fj. 1 and 2 shows the functional diagrams of the pulse counter in the p-Fibonacci codes (i); FIGS. 3 and 4 are timing diagrams for reading the operation of the counter.

The pulse counter contains the first elements OR 1-6, which are connected to the counting inputs of the counting triggers 7-12, the first elements AND 13-18, the second elements AND 19-24, the triggers 25-30, the third elements G 31-36, the second element OR 37, D-flip-flop 38, the HE element 39 and the delay element 40.

Trigger 7 corresponds to the youngest bit of the counter, and trigger 12 corresponds to the oldest.

Each i-th bit (, 2 ,, .., p) contains a counting trigger, the first element OR, the first element AND, the first input of which is connected to the inverse output of the counting trigger, the direct output of which is the information output of the counter and connected with (K + 2) -th input (, 2 ,, .., P + 2) of the first element AND (i + K) -ro bit. Each bit also contains a second And element, a trigger, a third And element, the first input of which is connected to the direct output of the trigger, and the second input is connected to the counting input 41 of the device, the input of the HE element 39, the input of the delay element 40, the output of which is connected to the first input of the second element is And, the second input of which is еди

00

to

314

pen with a direct output of the counting trigger, the inverse output of which is connected to the third input of the second element AND (i + l) -ro discharge and the fourth input of the second element AND (i + P + l) -ro discharge, except (P + 2 ) and (P + 3) -th bits, the fourth input of the second element And (P + 3) -th discharge is connected to the inverse output of the counting trigger 7 of the first discharge, the output of the second element And is connected to the second input of the trigger, the first the input of which is connected to the output of the first element AND, the output of the third element AND the 1st bit is connected to the first input of the first element OR the 1st bit, in The first input of the first element OR (il) -ro bit and the third input of the first element OR (1-G-1) -th bit, except for the first and second bit, the output of the third element AND () -th bit connected to the third the input of the first element OR 1 of the first bit, the trigger output of the 1st bit is connected to the i-th input of the second OR element, the output of which is connected to the first input of the second element AND and the input of the D-flip-flop 38, the synchronous input of which is connected to the output of the HE element 39 and the second input of the first element And, the initial Input (not shown in the diagram) installation is connected to the input n The initial installation of the counting trigger and the D-flip-flop, the output of which is the failure output of the device.

Any natural number can be represented by the formula

,, cfp (n) + a ,, (n-l) + ... + a04 P (0) 1

(About where a is the value of the binary digit

1st bit;

Ifp (i) is a generalized Fibonacci number, which is defined as follows: Γ 0 for i 0;

tCp (i) {1 with i 0;

{ifpO -O + M pCi-p-O with i 0

The representation of numbers in the form of expression (1) is called the Fibonacci redundant number system.

The HE element 39, at the input of which a counting pulse arrives, forms at the output an inverse counting pulse, which is fed to the input of the first and second elements AND bits. The signal from the output of the first element And is fed to the input of the trigger, the output of which determines

one"

switching of counting triggers. The second element And, to the inputs of which signals from the outputs of the counting triggers are received, controls the switching of the counting triggers and controls the operation of the triggers. The third element, AND, to the input of which a counting pulse arrives, forms an output signal that defines the excitation function of the counting triggers. The D-flip-flop, on one input of which the signal comes from the output of the second element I, and on the second - an inverse counting pulse, generates an output signal that determines the failure of the device. Operational control is performed on a causal basis of a convolution operation.

Consider the operation of the pulse counter in p-Fibonacci codes (). Let for example, in the initial state in the counting triggers 7, 8, 9, 10, 11 and 13 code 000000 is recorded. The single signal from the output of the element NOT 39 enters the second inputs of the first elements And 13-18, The single signal from the inverse output of the counting trigger 7 is fed to the first input of the first element And 13 to the third input of the second element And 20, and to the fourth input of the element And 22. A single signal from the inverse output of the counting trigger 8 is fed to the first input of the first element And 14 and to the third input of the second element And 21. A single signal from the inverse output of the counting trigger and 9 is fed to the first input of the first element AND 15 to the third input of the second element I 22 and to the fourth input of the second element I 23. The single signal from the inverse output “of the counting trigger 10 goes to the first input of the first element I 1b 23 and the fourth input of the second element AND 24. A single signal from the inverse output of the counting trigger 11 is fed to the first input of the first element AND 17 and to the third input of the second element I 24. Zero signals from the direct outputs of the counting trigger trigger to the second input of the second element And 19-24, the first input of which receives x-zero signal output from the delay element 40. At the direct output of the trigger 25, there is a signal of a logical unit, which is fed through the second element OR 37 to the input of the D-flip-flop. From 5114

A counting pulse at the output of the third element And 31 generates a signal of a logical unit, which through the first element OR I is fed to the counting input of the counting trigger 7. The counter is set to the state 100000. Later, the resulting code combination is monitored. A delayed counting pulse arrives at the first input of the second element AND 19, and a single signal from the direct output of the counting trigger 7 arrives at the second input. A single signal is generated at the output of the second element And 19, which triggers the zero signal to zero. the trigger 25 is fed through the second element OR 37 to the input of the D-trigger 38, at the output of which a zero signal is generated. At the end of the counting pulse, a zero signal is generated at the output of the D-flip-flop, which characterizes the correct operation of the device.

Further operation of the device is illustrated in Table 1 and Fig. 3.

Pulse counter when operating in the same way. Its functioning occurs in accordance with table 2.

Consider the operation of the pulse counter in the Fibonacci p-codes () when the fourth digit counting trigger is incorrectly triggered, i.e. Trigger 28 does not go to the single state; Trigger 28 should trigger for the first time when the seventh counting pulse arrives at the counting input of the device. Therefore, the pulse counter, when counting the first six pulses, operates in accordance with the device operation algorithm. Thus, in this case, the state of the device can be taken as the initial state of the counter after counting the first six pulses. Consequently, after the termination of the sixth counting pulse, the counting triggers 7, 8, and 9 are in one state, the counting trigger 10, the triggers 25, 26, and 27 are in the zero state. At the output of D flip-flop 38, there is a logical zero signal. Along the trailing edge of the sixth counting pulse, the trigger 28 is transferred to one state. A single signal from the direct trigger 28 is fed to the first input of the third ele16

And 34. When a seventh counting pulse arrives at the counting input of the device, a single signal is generated at the output of the third element 34 and passes through the first elements OR 1, 3 and 4 and arrives at the counting input of counting triggers 7, 9 and 10. Counting triggers 7 and 9 is set to the zero state, and the counting trigger 10 will remain in the zero state, due to the conditional malfunction in operation. Thus, at the end of the seventh counting pulse, a zero signal remains at the output of the second element And 22, due to which the trigger 28 remains in the single state. A single signal from the trigger 28 is fed through the second element OR 37 to the input of a D-flip-flop, the output of which produces a single signal indicating the presence of a failure in the device. The timing diagram of the operation of the device when a failure is detected in the fourth bit is presented in FIG. 4.

Thus, failure is controlled to a constant zero and a constant unit of all elements, with the exception of monitoring the failure to a constant zero of the first AND element and the trigger, which determines a positive effect.

Claims (1)

Invention Formula The pulse counter in the Fibonacci p-codes, containing in each i-th digit de (, 2, .. ,, п) is a counting trigger, the first element is AND, the first element OR whose output is connected to the counting input of the trigger, the inverse output of which is connected to the first the input of the first element And, the direct output of the trigger is connected to the (K + 2) input (K 1,2, ..., P + 2) of the first element K (i + K) -ro of the discharge, characterized in that , in order to ensure control of the authenticity of the account, additionally contains a delay element, a NOT element, a second OR element, a D-flip-flop and in each bit of the second element три a flip-flop the third element And, the first input of which is connected to the forward output of the trigger, and the second input is connected to the counting input of the device, the input of the element NOT, the input of the delay element, the output of which is connected to the first input of the second element And, the second input of which is connected to the first output of the counting trigger , the inverse output of which is connected to the third input of the second element AND (i + l) -ro discharge and the fourth INR. of the second element AND (}, + +) -th digit, except for (P + 2) -th and (P 3) -Fr bits, the fourth input of the second element And (P + 3) -th bit is connected to the inverse of you the course of the counting trigger of the first bit, the output of the second element I is connected to the second input of the trigger, the first input of which is connected to the output of the first element AND, the output of the third element AND the i-ro bit is connected to the first input of the first element OR i-ro time Table 1 p yes, the second input of the first element OR (i-l) -ro bit and the third input of the first element OR (i-P-l) -ro bit, except the first and second bits, the output of the third element AND (P + 3) -th bit is connected to the third input of the first element OR of the first bit, the output of the trigger of the i-bit position is connected to the i-th input of the second element OR, the output of which is connected to the input B - Trz1rgger, the synchronous input of which is connected to the output of the element NOT and the second input of the first element Yiwu is the input of the initial installation connected to the input of the initial installation of the counting trigger and the D-trigger, the output of which is the failure output, table 2 Fig 2. CIL SI3 t T25 1480121 i jji ™ jyL jb-jyi JJi -JTL-W17P-- M% -LJ-L sh Fig.Z T7 G 26. Tv T27. TK