SU1479940A1 - Median filter - Google Patents

Abstract

The invention relates to specialized means of computing and can be used in the construction of digital communication systems. The aim of the invention is to simplify the median filter. For this purpose, a programmable memory block and a sequential approximation register are introduced into the median filter. The filter contains N registers 1, N comparators 2, a block of 3 permanent memory, a switch 4 and a register 5 of sequential approximation. 1 ill., 1 tab.

Description

four

CO CO 4

one

The invention relates to specialized means of computer technology and can be used in the construction of digital communication systems.

The aim of the invention is to simplify the filter.

The median filter is shown in the drawing.

The filter contains n registers 1, n comparators 2, block 3 of permanent memory, switch 4 and register 5 of successive approximation. The outputs of registers 1 are connected to the first information inputs of comparators 2, the outputs of which are connected to the address inputs of the fixed memory unit 3, the outputs of block 3 are connected respectively to the fixed contacts of the switch 4, the moving contact 20 of the zooming device and

4799402

in comparators 2. The results of the comparison are fed to the input of block 3. In accordance with formula (1), the output of block 3 can yield the value yef 1 if the number of input numbers satisfying condition d; 2 ™ - 1 is greater than or equal to the number b, or yB (0, if the number JQ of the input numbers satisfying the condition d; -1 is less than the number b, where 1 i N; d is the input binary number.

Thus, at the output of y e block, the value of the highest

15

ka

bit size dB Value

those)

(i.e., the value of y on the first so from the output of block 3 enters the information input of the register after

which is connected to the information input of the register 5 sequential approximation.

Block 3 is programmed according to formula (1), while the information outputs provide for the transformation of the combination at address outputs A ,, ..., A ":

1 at 0 at

Uh

 (

Aa +.

An-b;

+ Aa +,

+ Ap,

(one)

where b is the number of the order statistics 1 b;

y is the information output of block 3, corresponding to the order statistics of b; n is the number of filter registers; A, ... An - the state of the address inputs of block 3.

The device works as follows.

The number of the order statistics b is set by the switch 4. Binary numbers are fed to the input of registers 1. From the output of registers 1, binary numbers are fed to the first inputs of comparators 2. To the second inputs of comparators 2, a sequence of binary numbers is received from the output of register 5 of consecutive approximation. - 1 011 .. .1, where m is the number of bits of the serial approximation register 5, which is compared with the input numbers

five

0

five

step of the second clock pulse is stored in the high order of the de sequential approximation register, at the output of which a binary number appears

Uv | 01 ... 1.

The sequence of binary numbers generated by the sequential approximation register is given in the table (where m is the number of bits).

The use of a median filter, for example, in digital television systems, in noise reduction devices will, compared to the prototype, reduce the number of digital comparators required for this task.

Claims (1)

Invention Formula A median filter containing n registers whose outputs are connected respectively to the first information inputs of n comparators, which is characterized by the fact that, for the sake of simplicity, the median filter contains a block of a fixed memory, a sequential approximation register and a switch, while combined and connected to the output of the sequential approximation register, whose information input is connected to a moving contact Connected respectively to the information outputs of the permanent memory unit, whose address inputs are connected respectively to the comparators outputs, information inputs and registers are information inputs of the filter, the clock input of the sequential approximation register 1 2 2 3 J Bf v -1 61 m m + 1 m + 2 81 l is the clock input of the filter, the output of the serial approximation register is the information output of the device. one ABOUT vg 1 o  in UVZ one Ye 1