SU1479938A1 - Queueing system simulator - Google Patents

Abstract

The invention relates to computing and can be used in the study of queuing systems (QS.) The purpose of the invention is to improve the accuracy of modeling. To this end, the device introduced a trigger for setting the operating mode, the second generator of the current, the third and fourth switches. 3 il.

Description

The invention relates to computing and can be used in the study of a queuing system.

The aim of the invention is to improve the accuracy of the simulation.

Figure 1 shows the diagram of the device; Fig. 2 is a diagram of the first switch of the application, the first block of modeling the queue and the first block of determining the number of occupied channels; FIG. 3 is a block diagram of a random time delay.

The device contains the first 1 and second 2 generators of the application, the first 3 and third 4 probabilistic switches, the first 5 and second 6 commutators, the first 7 and second 8 blocks of random time delay, the second 9 and fourth 10 probabilistic switches, the first 11 and the second 12 blocks for determining the number of occupied channels, the first 13 and second 14 blocks of the queue modeling, the mode setting trigger 15, the first 16, the second 17, the third 18 and the fourth

19 counters for the denied service counters, the first 20, second 21, third 22 and fourth 23 counters of the refusal service denied due to channel failure, the first 24 and second 25 reverse queue length counters, counters 26, 27 for wok

Switchboards 5, 6, 6 contain the first 28 and third 29 OR elements, the first 30 and third 31 prohibition elements, the second 32 and fourth 33 OR elements, the second 34 and fourth 35 And elements, the fourth 36 and second 37 prohibition elements, the sixth 38, Fifth 39, first 40 and third 41 elements I.

The block for determining the number of occupied channels contains a reversible counter 42, the element AND 43 and the element OR 44.

The block for modeling the queue contains the second element I 45, the second r the delay element 46, the first prohibition element 47, the third element 48, the first element 49 and the reversible counter 50, the decoder 51, the ele group (

(L

with:

J

with

CO CO 00

 And 52, the shift register 53, the first 54 and the second 55 delay elements, the first 56 and second 57 elements OR.

The random time delay block contains delay channels 58, delay channel start nodes 59.

Each delay channel contains the first element And 60, the generator 61 waste, the second element And 62, the first 63 and the second 64 elements of the random delay, the sixth 65 and the seventh 66 elements And, triggers Ј7-69, the fourth 70 and the third 71 elements And, the first 72 and the third 73 elements OR, the fifth element And 74, the element 75 prohibition, the eighth element And 76, the third element 77 delay.

Each node of the start of the delay channels consists of an element OR NOT 7 elements NOT 79 and an element OR 80.

Blocks 7, 8 also include the first 81 - sixth 86 elements OR.

Blocks 7, 8 work as follows.

In the initial state, the triggers 69 and 67 of all the channels are in a single state. At the same time, the triggers 69 provide zero potentials at the outputs of the OR-HE elements of 78 channels with numbers greater than or equal to the number of the trigger 69. To open each of the AND 60 and 62 elements, a single potential is required from the output of the corresponding OR-NOT 78 element. if one of the channels is free, the possibility of the passage of a pulse imitating the flow of a request to the inputs of channels with large numbers is excluded. The pulse received at the input of block 7, through the open element And 60 of the first channel 58, through the element OR 73 will pass to the zero input of the trigger 69 and directly from the output of the element And 60 to the input of the element 63 (64) random delay until this pulse If the delay element 63 (64) does not appear, the trigger 69 of the first channel will be in the zero state and only the second channel element 60 (62) will be open. When the next pulse arrives, it will go to the input of the delay element 63 (64) and the mouth

Q c

Q

five

5 0 5

0

0

five

sets the corresponding trigger 69 to the zero state, and so on.

A pulse from delay element 63 (64), lurking at the output after a time equal to the random duration of service, the passage through the open (since the trigger. 67 is in one state), element AND 65 (66), element OR 72, will set the corresponding trigger 69 in a single state and simultaneously with the output of the element AND 65 (66) through the element OR 82 (83) will go to the second (third) output of the random time delay block

A generator 61 pulse, imitating a random stream of channel failures, passes to the input of delay element 77, which simulates the channel recovery process, through element OR 73 to zero input of trigger 69 imitating channel occupation, to zero input of trigger 67 and to input of element And 70, and if the channel was not in service (trigger 69 was in the single state), the AND 74 element is open and the pulse from the generator passes through the OR 81 element to the first output of the block of random time delays and signals that the channel is busy. If the channel was occupied by the service (trigger 69 in the zero state), the element 70 is opened and the generator 61 impulse arrives at the inputs of the element 76 and the inhibit element 75, and the pulse from the element 71 arrives simultaneously, if the trigger 68 is in unit condition. Then through the element And 76 and the element OR the signal is sent to the output unit of the random time delays, which simulates a denial of service for applications of the second type due to a failure in the channel. If the trigger 68 is in the zero state, then the output of the And 71 element will be zero, it opens the inhibit element 75 and the pulse from the And 70 element through the OR 84 element arrives at the output of the block 7 random time delays, simulating a failure of the first type of application for failure in the channel. The initial state of the trigger 68 is zero. The trigger 68 is set to one state by a pulse from the output of the element 62, imitating the start of service of the second type of application, and is reset to the zero state by a pulse from the output of the element of the random time delay, indicating that the second type of application has served.

In this case, the pulse that appeared at the output of the element 63 (64) of the random delay will not be able to pass to the output of the block a random time set on the counter 16 (17) of the number of wok that have been denied service. If the queue is not overfilled, then the output of the element And 49 is set to the signal of the zero level and the pulse through the open element of the prohibition 37 (36) from the output of the elements And 40 (41) is fed to the summing input rever

due to the zero state of the triggered-JQ counter 24 (25) number of zager 67. To eliminate the appearance of a false pulse at the output of element 63 (64) after the channel is restored, the signal delay in element 77 must be significantly greater than the delay in element 63 (64).

The pulse at the output of the delay element 77, which appeared after a random time equal to the random duration of the channel recovery, arrives at the single input of the trigger 69 and at the same time through the OR element. 86 at the output of a block of 7 random time delays, thereby simulating the restoration of the service channel.

The remaining channels work similarly.

Blocks 5, 6, 11, 12, 13,14 work as follows.

The impulse from generator 1 (2), or from probabilistic switches 9, 10, or from open element AND 39 (38) goes to element OR 28 (29), from the output of which it goes to the inputs of prohibition elements 30 (31) And 40 (41), if there are free channels, that is, at the output of block 11, the signal is zero, the pulse through the open prohibition element 30 (31) is fed to the inputs of the OR 32 (33) and OR 44 elements. From the output of element 44, the signal arrives on the summing input of the reversing counter 42 the number of channels occupied. If all the channels are occupied, the output of element 43 is set to a single level signal, prohibition elements 30 and 31 are closed, and elements 40 and 41 are opened.

The next pulse from generator 1 (2) through the element OR 28 (29) goes to the open element AND 40 (41), from the output of which goes to the first input of the elements And 34 (35)

and prohibition 37 (36). If the queue is full, then the second inputs of the elements And 34 and 35 and prohibition 36 and 37

.with the output of the element And 49 a signal of a single level will arrive and will open the elements And 34 and 35. Then the impulse of the trips in the queue of one type is also at the output of the element OR 57, from the output of which the impulse goes to the summing input of the reversible counter

15 50 total quotes for queuing; From the output of the element 37, a pulse arrives at the element 55 of the delay, the delay time of which is equal to the time of changing the content of the counter 50 per unit plus the time of changing the output of the donorfrator, on which a single signal is set. After this time from the output of the element 55 of the input delay Assembly

25 element gates And 52 enters

entry resolution strobe, which solves the entry of a unit into register bit 53 with a number equal to the number of requests in the queue.

3Q In the event that the second type of input goes to the input of the element OR 29, then the unit record does not occur and zero is stored in the category with the number equal to the number of the request in the queue. The signal from the first output of the block 7 random time delays, meaning that one of the channels failed, goes through the OR 44 element to the summing input of the reversing counter 42 of the number of occupied channels.

35

40

The signals from the second and third output of block 7 (8) of random time delays, meaning that the service was processed for the first or second type, respectively, through probabilistic switches with probability (1-p) are fed to switch 6. The outputs of switches 34 are connected to

50 inputs of the OR element 56. If there is no queue and at the first output of the decoder 51 a single level signal that opens the AND 48 element and closes the prohibition element 47, then the pulse55 from the output of the OR 46 element passes through the 48 element to the subtracting input of the reversing counter 39, which indicates that one channel is free. If there is a queue in the same type queue, the output of the OR 57 element, from the output of which the pulse goes to the summing input of the reversing counter, is also output

50 total quotes per line; From the output of the element 37, a pulse arrives at the element 55 of the delay, the delay time of which is equal to the time of changing the content of the counter 50 per unit plus the time of changing the output of the donatfrator on which the unit signal is set. After this time from the output of the element 55 of the input delay Assembly

gates of elements And 52 enters

entry resolution strobe, which allows the unit to be written to register bit 53 with a number equal to the number of queued items in the queue.

If the second type of input is received at the input of the element OR 29, then the unit is not recorded and zero is stored in the discharge with the number equal to the number of the quota in the queue. The signal from the first output of the block 7 random time delays, meaning that one of the channels failed, goes through the OR 44 element to the summing input of the reversing counter 42 of the number of occupied channels.

The signals from the second and third output of block 7 (8) random time delays, meaning that they served the first or second type of application, respectively, through probabilistic switches with probability (1-p) are fed to switch 6. The outputs of switches 34 are connected to

the inputs of the element OR 56. If there is no queue and at the first output of the decoder 51 a single level signal that opens the element AND 48 and closes the prohibition element 47, then the pulse from the output of the element OR 46 through the element 48 goes to the subtracting input of the reversing counter 39, which indicates that one channel is released. If there is a queue, prohibition element 47 is opened and E 48 is closed. Then the pulse from the output of block 56 goes to the subtracting input of the reversible counter 50, to the input of the shift of the register 53 and to the input of the delay element 43. After addition to As in register 53 there will be a shift, the elements of And 45 and prohibition 46 will be given a signal of a single level if the turn of the second type of application has arrived. From delay element 54, a pulse passes through an open prohibition element, if the application is of the second type. Thus, the signal at the output of the And 45 element means that the first type was selected from the queue, and the signal at the output of the prohibition 46 element means that the second type was chosen from the queue. The pulse from the element And 45 enters the element OR 32 (33), from which enters the input of the block 7 random time delays.

The trigger 15 controls the operation of the elements And in such a way that applications that are interrupted during maintenance re-enter the probability switch.

The accuracy characteristics of the system are determined by meter readings.

Claims (2)

1. A device for simulating queuing systems, comprising a first generator of the application, first and second blocks of a random time delay, first and second probabilistic switches, first and second blocks of queuing modeling,  each of which consists of a reversible counter, two OR elements and two AND elements, two blocks for determining the number of occupied channels, each of which contains an OR element, a reversible Counter and an AND element, whose inputs are connected respectively to the discharge outputs of the reversible counter, the first and the second switch is a switch, each of which contains the first and second elements OR, the first and second elements AND, the first and second elements of the ban, the output of the first generator of the order is connected to the first input of the first element OR of the first comm Tatorey for wok, an output of first OR-in each switch applications are connected to data input per0 five 0 five 0 five 0 five 0 five the first barring element and the first input of the first element AND whose output is connected to the information input of the second prohibition element and the first input of the second element AND of its own switch, the control input of the second prohibition element and the second input of the second element And in each switch; to the output of the first element And, respectively, of the first and second blocks of the modeling queue, the inputs of the first element And in each block of the modeling of the queue are connected respectively to the discharge outputs of the reversible , the counter of its block for modeling the queue, in each switch for the wok the output of the first interdiction element is connected to the first input of the second element OR of its switch for the wok, the second input of the second element OR of the first and second switches for the wok is connected to the output of the second element AND of the first and second blocks respectively the queue modeling, the outputs of the second OR elements of the first and second switches of the terminal are connected to the first information inputs of the first and second random time delay blocks, respectively, For the first time, the outputs of the served applications of the first and second random time delay blocks are connected to the inputs of the first and second probability switches, respectively, the first and second informational outputs of the first probability switch are connected respectively to the inputs of the first OR element of the first queue modeling unit, and the first and second information blocks the outputs of the second probabilistic switch are connected respectively to the inputs of the first element OR of the second block of the modeling of the queue, in each block of determination the number of channels occupied — the output of the element OR is connected to the summing input of the reversible counter; the control input of the first prohibition element and the second input of the first element AND in the first and second switch are combined and connected to the output of the element AND, respectively, of the first and second blocks of determining the number of occupied channels, characterized in that, in order to improve the accuracy of modeling, it additionally contains a trigger setup operation mode, the second generator of the calls and the third and fourth probabilistic switches, and each switch of the order additionally includes from the third to the sixth elements AND, the second and third elements of OR, the third and fourth elements of the prohibition, each block of modeling the queue additionally contains the third element And, a group of elements And, the first and second elements of the prohibition, two delay elements, a decoder and a shift register, and the output of the second generator is connected to the first input of the third element OR of the first switch, and to In the switch switch, the output of the third OR element is connected to the first input of the third AND element and the information input of the third prohibition element, the output of which is connected to the first input of the fourth OR element, the output of the third AND element is connected to the first input of the fourth AND element and the information input of the fourth prohibition element, the outputs of the fifth and sixth elements And are connected to the second inputs of the first and third elements, respectively, OR, the first inputs of the fifth and sixth elements And both switches of the order are combined and five Connected to the direct output of the device mode setup trigger, the inputs of which are the installation inputs of the device, in each block of the queue simulation the output of the first element OR is connected to the information input of the first prohibition element and the first input of the third element And the second input of the coyur and control input of the first the prohibition element is combined and connected to the first output of the decoder, the remaining outputs of which are connected to the first inputs of the AND elements of the group, respectively, the outputs of which are connected respectively but to the bit inputs of the shift register, the shift input of which, the subtract input of the reversible counter and the input of the first delay element are connected to the output of the first prohibition element, and the output of the first delay element is connected to the first input of the second And element and the information input of the second prohibition element, the control input which and the second input of the second element And are connected to the output of the last digit five 0 five 0 five 0 five 0 five the shift register, the output of the second delay element is connected to the second inputs of the AND elements of the group, and the output of the second element OR is connected to the summing input of the reversible counter, the discharge outputs of which are connected respectively to the inputs of the decoder, the outputs of the fourth inhibit element of the first and second switches are connected to the first the inputs of the second OR elements, respectively, of the first and second blocks of the queue modeling, the second inputs of the second OR elements of which are connected to the outputs of the second prohibition elements respectively Actually, the first and second switches of the application, the inputs of the second delay elements of the first and second blocks of the queue modeling are connected to the outputs of the second prohibition elements of the first and second switches, respectively, the outputs of the fourth elements And the first and second switches of the first and second switches, respectively. the outputs of the quota, which are not accepted for service, and the outputs of the second elements of the first and second switches of the quota, respectively, are the third and fourth outputs of the quota, which are not accepted for servicing the devices, the outputs of the second prohibition elements of the first and second blocks of the queue modeling are connected to the second inputs of the fourth OR elements of the first and second switches, respectively, the outputs of the fourth OR elements of the first and second switches of the station, are connected to the second information inputs of the first and second, respectively random time delay blocks, the outputs of the fault signals of which are connected to the first inputs of the OR elements of the first and second blocks for determining the number of occupied channels, respectively, the second inputs of the OR elements which are connected to the outputs of the first prohibition elements of the first and second switches of the equipment, respectively; the third elements And, respectively, of the first and second blocks of the queue modeling, the second outputs of the first and second blocks served by the random block The second delays are connected to the inputs of the third and fourth probability switches, respectively, the first and second outputs of the third probability switch are connected to the third and fourth inputs of the first block of the modeling queue respectively, and the first and second outputs of the fourth probability switch are connected to the third and fourth inputs of the first the OR element of the second queue modeling unit; the outputs of the restoration signals of the first and second random time delay blocks are connected to the fifth and the inputs of the first elements OR, respectively, of the first and second blocks of the modeling turn, the first outputs interrupted in service of the first and second bids thirty 40 The random time delay block 25 is connected to the second input of the second element OR, the input of the second element of a random delay, to the single input of the second trigger, the output of the fault generator is connected to the input of the third element of the random time delay and to the first inputs of the third, fourth and fifth elements And with the zero input of the third trigger, the output of the third random delay element is connected to the first input of the first OR element and to the single input of the third trigger, the direct output of the first trigger is connected to the third one. the input of the fifth element And the second input of the fourth element. And connected to the inverse output of the first trigger, the output of the first element of the random delay is connected to the first input of the sixth element And, the output of the second element of the random delay is connected to the first input of the seventh element And, the direct output of the third trigger And connected to the second element random delay is connected to the first input of the seventh element And, the direct output of the third trigger is connected to the second inputs of the sixth and seventh elements And, the output of the second element of the random delay is connected to the zero input of the second trigger, the direct output of which is connected to the second input of the third element I, the output of which The ki are connected to the second inputs of the fifth elements And, respectively, of the first and second switches of the application, and the second outputs of the first and second blocks of random delay interrupted in the maintenance of the equipment are connected to the second inputs of the sixth elements And, respectively, of the first and second switches, the output of the element And the first unit is defined. Not the number of channels occupied is connected to the control input of the third prohibition element and the second input of the third element AND of the first switch of the subscription, and the output of the element AND of the second block for determining the number of channels occupied is connected to the control input of the third prohibition element and the second input of the third prohibition of the second switch element of the quota, in the first and second switch of the wok, the second inputs of the fourth AND elements and the control inputs of the fourth prohibition elements are combined and connected to the outputs of the first AND elements of the first and VT respectively queue modeling units, the first outputs of the first and third probability switches are connected respectively to the second inputs of the first and third OR elements of the second switch, and the first outputs of the second and fourth probability switches are connected respectively to the second 45 50 55 479938 mi 12 ten the inputs of the first and third elements OR the first switch for the wok. 2. Pop-up device 1, characterized in that the random time delay block contains six OR elements, the outputs of which are respectively the first to sixth outputs of the block, M delay channels and (M-1) delay channel trigger nodes, each delay channel includes eight elements AND, a prohibition element, two elements OR, three trigger-15 Pa THREE elements of random delay and a generator of failures, in each channel of the delay the outputs of the first and second elements of the OR channel of the delay are connected respectively to the single and zero inputs of the first three gage, the output of the first element AND is connected to the first input of the second element OR and the input of the first element of a random delay, the output of the second element 20 connected to the first input of the eighth element AND and the control input of the prohibition element, whose information input and the second input of the eighth element AND are connected to the output of the fourth element AND, the outputs of the sixth and seventh elements AND are connected respectively to the second and third inputs of the first element OR, direct output the first trigger of the first delay channel is connected to the second inputs of the first and second AND elements of its delay channel; the delay channel triggering node contains an OR element, an OR-NOT element, and an NO element whose output is connected n with the first input of the element OR-NOT, the outputs of the fifth elements AND delay channels are connected respectively to the inputs of the first element OR block whose output is the output of the block failure signals, the outputs of the sixth elements AND delay channels are connected respectively to the inputs of the second element OR block, the output which is the first output of the served block queuing, the outputs of the seventh elements and the delay channels are connected respectively to the inputs of the third element OR block, the output of which is the second output of the served block Loka, the outputs of the eighth elements And the delay channels are connected respectively to the inputs of the fourth element OR block, the output of which is the first output of the interrupted service in the service; interrupted five 0 five 0 five 0 In the servicing request, the outputs of the third random delay elements of all the delay channels are connected respectively to the inputs of the sixth OR element of the block whose output is the output of the block recovery signals, the second inputs of the first And delay channel elements are combined and are the first information input of the block, the second inputs The second And elements of all delay channels are combined and are the second information input of the block; the direct output of the first trigger of the first delay channel is connected to the second input of the IL element -NOT and the first input of the OR element of the first node of the launch of the delay channel, the direct output of the first trigger of the K-th delay channel (K 2, ..., M-1) is connected to the input of the element NOT and the second input of the element OR (K-1) th start node of the delay channel, direct output of the first trigger of the M th delay channel connected to the input of the NOT element (M-1) of the start node of the delay channel, the output of the OR element (K-1) of the starting node of the delay channel connected to the second input of the element OR NOT and the first input of the element OR of the K-th start node of the delay channel, the output of the element OR (M-2) -th node of the start the delay channel is connected to the input of the element OR — NOT (M-1) -th node of the start of the channel of the delay connected to the input of the element OR — NOT (m-1) of the start node of the delay channel, the output of the element OR — NOT (K-1) - The first node of the start of the delay channel is connected to the first inputs of the first and second elements of the K-th delay channel. 1 Qm5 / i. 15 From 5/1. one From5 9 Omd / i. ten thirty Qmfa.2 -ifllpiL  f f y one L. 37   V f I 55 . Kb / 1.16 kb / 1.17 Kff / i. 20.21 whose 42 L. Hhh fe eleven THOSE To fa. 6 K $ / 1.6 7 56 13 ll T- 55 F 50 51 51 55 FIG I