SU1478332A1 - Shaft encoder - Google Patents

Abstract

The invention relates to automation and computing and can be used to connect analog information sources with a digital computing device. In order to increase speed when processing large discrepancies between the angle α and the code β in the shaft angle converter, the code contains a sine-cosine angle sensor (MCDD) 1, a reference voltage source 2, digital-to-analog converters (DAC) 3 and 4, block 5 Inverters, Nonlinear Code Conversion Unit 6, Voltage to Frequency Conversion Unit (PNC), Sample Storage Unit 8, Control Unit 9, Switch 10, Amplifier 11, Reversible Counter 12, Integrator 13 and Conversion Rate Driver 14 are entered. The output signals of SKDU 1, modulated in amplitude as a function of the sine and cosine of the angle α, are fed to the analog inputs of the D / A converter 3 and the DAC 4, to the digital inputs of which the reversing counter 12 is fed through the block 5 in the summing amplifier. angle α and code N. In block 7, pulses are generated with a frequency proportional to the output voltage of the integrator 13. The output pulses of block 7 of the FPU are fed to the input of the reversing counter 12. Depending on the value of the output voltage of the integra Ator 13, unit 14 generates a code for the conversion factor of the reversible counter 12, thereby changing the speed of the turning angle and the resolution of the converter. 1 hp f-ly, 5 ill. 2 tab.

Description

The invention relates to automation and computing and can be used to communicate analog; sources of information with a digital computing device.

The aim of the invention is to increase the speed of the converter during the development of large mismatches between the angle and the code.

Figure 1 shows a block diagram of a converter; figure 2 - structural diagram of the driver conversion factor; FIG. 3 is a structural diagram of a reversible counter; Fig. 4 is a block diagram of the control unit; on fig.Z - temporary chart of his work,

The shaft rotation angle converter into the code (FIG. 1) contains a sine-cosine angle sensor (SKDU) 1, a reference voltage source 2, analog-to-digital converters (D / A converters) 3 and 4, an inverter unit 5, a nonlinear code conversion unit 6 , a voltage-to-frequency (VLF) conversion unit 7, a sampling-storage unit 8, a control unit 9, a switch 10, an amplifier 11, a reversible counter 12, an integrator 13, and a conversion factor driver 14. The conversion factor generator 14 (FIG. 2) contains rectifier 15, bias voltages 16 and 17, comparators 18 and 19, elements K 20 and 21, inverters 22 and 23, element OR 24, reversible counter 25, reversible counter (FIG .3) contains reversible counters 26-28 and blocks 29 and 30 of memory, which are blocks of non-linear conversion of codes. The control block 9 (FIG. 4) contains a comparator 31, the elements Exclusive OR 32 and 33, a single vibrator 34 and 35,

The Converter operates as follows.

At the output of ACS-1, AC signals are generated modulated in amplitude as a function of the sine and cosine of the angle 0 of the rotation of the rotor SKDU-1, which in HAP 3 and D / A 4 are multiplied by the forward | 3 or inverse (1- / 3) development codes quadrant angles coming from the outputs of block b,

The output voltage of the DAC 4 delivers through the switch 10, depending on the number of the quadrant of the working angle / 3 to the summing (in the 2nd, 4th quadrant) or subtracting (in the 1st, 3rd square)

e

five

four

0 5 0, Q

Q

five

five

welt) summing amplifier input

11, The quadrant number is determined by the code of the higher n and (n − 1) bits of the reversible counter 12, which varies from 00 in the first quadrant

to 11 in the fourth quadrant.

Output signal summing amplifier .11, equal to °

UH () sinei-JicosuTju sinot, fed to block 8. In KOTODOM, the amplitude Un is memorized by a sampling pulse from control block 9.

In accordance with the polarity and magnitude of the output voltage of the integrator 13, the pulses produced in the VLF block 7 are sent to the direct or inverse input of a reversible counter

12. The control pulses of block 8 are produced in control block 9 in accordance with the quadrant number of the working angle B so that if the angle B is located in the first or fourth quadrant, then the sampling time coincides with the positive half-wave reference voltage of source 2; located in the second or third quadrant, then the sampling moment falls on the negative half-wave of the reference voltage. This ensures that the shortest distance to one side is worked at, located in the first or second quadrant, or in the other direction at ui, located in third or four; vert quadrant.

The reduction of the methodological error of conversion

l

Snp P - arctg -pp

to zero is performed by block 6 of nonlinear code conversion, made in the form of a block of permanent memory, the address inputs of which receive a code (n-2) for lower-order bits of the reversible counter 12, and a corrected rotation angle ib is generated on the output buses,

If the angle oi varies with a constant speed, then the code p is processed without lag, if the maximum frequency of the output pulses of the FPU unit 7 is not exceeded. With a limited frequency of block 7, the rate of change of the angle O may be increased by reducing the resolution of the converter by changing the conversion factor of the reversible counter 12.

The generation of the necessary conversion factor is carried out in shaper 14.

The output voltage of the integrator 13 after straightening in rectifier 15 is applied to comparators 18 and 19, the thresholds of which are determined by the voltages on tons 16 and 17 and are respectively 5 UBM,, 25UBM, where U & m is the maximum output voltage rectifier 15 (transfer coefficient of rectifier 15 is taken equal to one). The change in the conversion factor, determined by the state of the reversible counter 25, occurs when the voltage of the rectifier U1S-Um or at the moments determined by changing the number of the quadrant angle of the working out on the negative edge of the output pulse (p-2) of the counter reversible counter 12, the rate of change of the angle of rotation of the SKDU-1 is such that Uni U15 UBM, then the comparator 18 is triggered and opens element 20. An impulse from the output (the n-2 bit of the reversible counter 12 passes through the inverter 22 and the element I 20 and to the input C1 of the reversible counter 25. Comp etstvenno with increasing number of outlet down counter 25 decreases the discharge of clarity reversible counter 12 by one significant bit, which corresponds to doubling the unit prices of the least significant bit conversion angle. mining speed increases.

The maximum number that can be recorded in the reversible counter 25 is 0111, since occurrence 1 at the output of the 4th bit of counter 25 causes, via an inverter 23 at input L, to record information 0111 present at the inputs of OA-AZ counter 25, that corresponds to the conversion factor.

Similarly, when the speed of change of the angle of rotation decreases and the corresponding output voltage of the rectifier 15 / U decreases, Un2 triggers a comparator 19, a pulse from the output (n-2) of the discharge of the reversing counter 12 through the inverter 22 and element I 21 passes to input C2 - reversible counter tane 25. The recalculation coefficient is halved, the size of the reversing counter

0

five

0

five

0

five

0

five

The pin 12 is increased, the tracking speed is reduced.

With a further decrease in the rate of change of the angle of rotation, the state of the counter 25 decreases to 0000, which is confirmed by a transfer pulse when the reversible counter 25 is output from the P2 output and is fed through the OR 24 element to the reset input of the reversible counter 25. The zero state of the reversible counter 25 Reverse counter 12.

When SKDU-1 suddenly stops, which rotates at a speed exceeding the tracking speed at the minimum discreteness, the output voltage of the integrator 13 becomes zero, which through the OR 24 element is fed to the reset input of the reversible counter 25, sets it to the zero state corresponding to the coefficient recalculation, i.e. The rotation angle is tested with the maximum resolution of the converter.

In a reversible counter 12 with a variable conversion factor (FIG. 3), the counting of the pulses of the FNP 7 is performed using two four-bit reversible counters 26 and 27 and the block 28 of reversible counters, and the change of the discharge code of the refining code in accordance with the required conversion factor is using a ROM 29 and 30, the address inputs A6 - A8 which receives signals from the generator 14 conversion factor. The programming of the ROMs 29 and 30 is carried out according to Tables 1 and 2, where junior and senior bits are used, respectively.

Claims (2)

Invention Formula 1, Shaft rotation angle converter into a code containing a sine-cosine angle sensor, the input of which is connected to the output of the voltage source, and the first and second outputs are connected to the analog inputs of the first and second digital-to-analog converters, the output of the first digital-to-analog converter connected to the first summing input of the amplifier, the output of the second digital-to-analog converter is connected to the information input of the switch torus, the first and second outputs of which are connected respectively to the second summing and subtracting inputs of the amplifier, the output of the amplifier is connected to the information input of the sample-storage unit, the voltage-to-frequency conversion unit, the output of which is connected to the information inputs of the reversible counter, low-voltage outputs of the reversible counter connected to the inputs of the nonlinear code conversion block and the information inputs of the inverter block, and the high-order outputs to a group of inputs of the control block, one input of which Connected to the output of the reference voltage source, and the output is connected to the control input of the sample-storage unit, the output of the lower-order high-order digit of the reversible counter is connected to the control input of the switch and the inverter unit, the first and second groups of outputs of which are connected to the digital inputs of the first and a second digital-to-analog converter, characterized in that, in order to increase the speed of the converter when processing large discrepancies between the angle and the code, a shaper of the coefficient is introduced into it recalculator and integrator, the input of which is connected to the output of the sampling-storage unit, and the integrator output is connected to the input of the voltage-to-frequency conversion unit and one input of the conversion factor generator, the other input of which is connected to the output of the higher low five 0 0 five 0 five a reversible counter, and the outputs are connected to the control inputs of the reversible counter. 2. The converter according to claim 1, wherein the conversion factor driver comprises a rectifier, two comparators, two bias voltage buses, two AND elements, an OR element, two inverters and a reversible counter, the rectifier input and the first inverter are respectively one and the other inputs of the conversion factor generator, the output of the rectifier is connected to the first inputs of the comparators and the OR element, the second inputs of the first and second comparators are connected respectively to the first and second bias voltage buses, and the output The first and second comparators are connected respectively to the first inputs of the first and second And elements, the second inputs of which are connected to the output of the first inverter, and the outputs are connected to the first and second counting inputs of the reversible counter, the outputs of the three reversible counter bits are the outputs of the conversion factor shaper , the output of the fourth bit of the reversibility of the counter through the second inverter is connected to the control input of the reversible counter, the transfer output of the reversible counter is connected to orym input OR gate whose output is connected to the reset input of down counter. Table 1  | 2 | s i 1 5 i & | 7 I 8 W 9 | YU eleven 13 {Ng 5 | "6 1 P 1 a C l and c a 2 fli-Mp m-dp tze 7t # / f-7j / 2tt 5