SU1478230A1 - Analog four-quadrant multiplier - Google Patents

Abstract

The invention relates to electrical computing devices and can be used in analog computers. The aim of the invention is to expand the dynamic range, increase accuracy and reduce power consumption. An analog four-quadrant multiplier contains three voltage-to-current converters, two current-voltage converters, two load resistors, twenty-four amplifying field-effect transistors, six adjustable bias voltage sources, twelve adjustable mains voltage sources, two power supply buses, and a reference voltage bus two input buses of the first signal multiplier, two input buses of the second signal multiplier, two output buses. The operation of the multiplier is based on the implementation of the variable steepness method. 6 Il.

Description

The invention relates to electrical computing devices and can be used in analog computers.

The aim of the invention is to expand the dynamic range, increase accuracy and reduce power consumption.

FIG. 2 is a functional diagram of an analog four quadrant multiplier; FIG. 2 is a functional diagram with first to fourth adjustable sources of bias voltage; in fig. 3 is a functional diagram of a fifth and sixth adjustable bias voltage source; in fig. 4 is a functional diagram of the first, second, fifth, sixth, eleventh, and twelfth regulated sources of mating voltage; in fig. 5 is a functional diagram of the third, fourth, and seventh to tenth controlled voltage sources; in fig. 6 is a plot of the output currents of the third voltage-to-current converter versus the input voltage (continuous line), as well as a graph of the transfer characteristic of the third voltage-to-current converter explaining its principle of operation (dashed line).

The multiplier contains the I figs, 1-4) first 1, second 2 and third 3

00

to

with

voltage converters to current, first 4 and second 5 current-voltage converters, first 6 and second 7 load resistors. from first to twenty fourth amplifying field effect transistors 8-31, first to sixth adjustable sources 32-37 of voltage displacement, from the first to the twelfth adjustable voltage sources 38-49, the first 50 and second power spikes 51, the reference voltage spike 52, the first 53 and second 54 input buses of the first signal multiplier, the first 55 and second 56 input tires of the second signal multiplier, the first 57 and the second 58 e tires, twenty-fifth fifth and twenty-sixth 60, amplifying field effect transistors, first adjustable bias current source 61, first 62 and second 63 pins, control input 64, twenty seventh 65 and twenty eighth 66 amplifying field transistors, second adjustable source 67 bias current, first 68 and second 69 pins, control input 70, from twenty-ninth to thirty-second amplifying field effect transistors 71-74, first adjustable source 75 of the current, first 76 and second 77 pins, control input 78, from the thirty-third thirty sh stand amplifying FETs 79-82, second adjustment current source 83 interface, the first 84 and second 85 terminals, a control output 86.

The multiplier works as follows,

The principle of operation is based on the variable slope method. When a third voltage converter 3 is applied to the input, the second signal-multiplier voltage at its outputs flows currents, the difference of which is described by the expression

I1-LL 4K3Јp (V0H-Vb2) Vv, (1) where 1ts, 1.1} - output currents of the third

voltage-to-current converter 3; fixed parameters; The voltage of the second signal multiplier; coefficient taking into account the steepness of field-effect transistors. In this case, the first output current of the third voltage converter 3 to the tech is through the first converter Bl V & 2 V ,,

TO

0

0

five

0

five

0

five

0

five

the current-voltage-4 transducer, which can be used as a diode-switched transistor (field or MIS), changes the steepness of the first voltage-current converter 1 due to a change in the voltage values between the first and second terminals of the first 32 and second 33 controlled sources the bias voltages of the first 38, second 39, third 40 and fourth 41 controlled voltage sources. At the same time, the second output current of the third voltage-to-current converter 3 through the second current-to-voltage converter 5 changes the steepness of the second voltage-to-current converter 2 due to a change in the voltage values between the first and second terminals of the third 34 and fourth 35 regulated voltage sources the offset and the fifth 42, sixth 43, seventh 44 and eighth 45 adjustable sources of voltage mate.

The corresponding values of the output currents of the first 1 and second 2 voltage-to-current transducers when the voltage of the first signal factor is supplied to their inputs are described by the expressions

C KEFO + UU + UH); is.K cva-Vy-v) 2;

(V6 + Vy-V, f; (2)

I9., (Vb-Vy + V, f, where I1M,,

 D2.2 currents at the outputs of the first 1 and second 2 voltage to current converters, respectively; V4 - voltage of the first signal multiplier,

The output current of the multiplier is described by

1y (IM + IU.) - (IU + II-B). (3)

Substituting .in (3) expression (2),

we get

1By 4K3opVxVy. (4)

The output voltage is described by the expression

Chyg 4K3cpR V, Vy,, (5)

where R is the resistance value of identical first 6 and second 7 load resistors. Figure 2 shows an example of the construction of the first 32, second 33, third 34 and fourth 35 controlled sources of bias voltage. The potential difference between the first 62 and second 63 terminals of the circuit (figure 2) is equal to

-fl / Kn + {l / K (

I / Kn + Nl / Kp + Vnepn + VnOPp, (6)

where I is the current value of the first controlled bias current source 61;

К „, Кр - slope, respectively, of twenty-five and 59 and twenty-sixth 60 amplifying field-effect transistors;

ULOR.P

POR P threshold voltages of these transistors.

The potential difference between the first 68 and second 69 pins of the fifth 36 and the sixth 37 adjustable bias voltage sources (Fig. 3) is described by an expression similar to expression (6).

FIG. 4 shows a functional diagram of the first 38 and second 39 adjustable voltage sources. When choosing the ratio of the channel width to the channel length of the twenty-nine amplifying field-effect transistor 71 is nine times smaller than the ratio of the channel width to the channel length of the thirtieth amplifying field-effect transistor 72, whose dimensions coincide with the channel sizes of the first 8 and second 9 amplifying field-effect transistors of the first converter 1 voltage to current, the voltage between the first 7-6 and the second 77 pins is determined by the difference of the gate-source voltages of the twenty-ninth 71 and thirtieth 72 amplifying field-effect transistors, which is

2t№ (7)

where I is the current value of the first controlled source 75 of the current.

The third 40 and fourth 41 adjustable voltage sources of the conjugation voltage (Fig.5) are similarly made.

When implementing an integral multiplier, the change in currents of all used controlled sources

782306

Current nicknames are proportional to temperature changes in the environment. In accordance with this, the voltages of the controlled bias voltage sources vary in proportion, which leads to the preservation of the conversion accuracy of the multiplier over a wide range of temperatures,

IQ Thus, in the analog four-quadrant alternator there is no connection between the conversion accuracy, the value of the current consumption and the value of the maximum permissible value.

15 input voltage This leads to the fact that the maximum permissible input voltage of the multiplier is limited only by the permissible parameters of the technological process.

2Q of the production of field-effect transistors: the voltage of the drain-source voltage, the voltage of the gate dielectric in the case of MIS transistors, as well as the voltage value

25 used power sources. In addition, a constant level of conversion accuracy is maintained throughout the entire voltage range used. The magnitude of the current consumption of the multiplications of the tel affects only the value of the bandwidth processed without distortion and does not affect the value of the conversion accuracy at different input voltage levels, i.e. the multiplier has a reduced power consumption.

Thus, the analog quad quadrant multiplier has an extended dynamic range,

40 increased conversion accuracy and reduced power consumption.

35

Claims (5)

1. An analog four-quadrant multiplier containing the first and second current-voltage converters, the first and second load resistors, the first voltage-to-current converter made on the first and second amplifying field-effect transistors of n-type conductivity, and the first and second adjustable sources bias voltage, second voltage to current converter, made on the third and fourth amplifying field-effect transistors of n-type conductivity and the third and fourth adjustable sources of bias voltage, the third converter voltage to current, made on the fifth and sixth amplifying field-effect transistors of p-type conductivity, and the fifth and sixth adjustable sources the bias voltages, the gates of the first and fourth amplifying field-effect transistors are connected to the first terminals of the second and third adjustable sources of bias voltage and are the first input bus of the first sy the multiplier multiplier, the gates of the second and third amplifying-field-effect transistors are connected to the first pins of the first and fourth adjustable sources of bias voltage and are the second input line of the first multiplier multiplier signal, the gates of the fifth and sixth amplifying field-effect transistors are connected to the first output sixth and fifth adjustable sources of bias voltage. are, respectively, the first and second input buses of the multiplier multiplier signal, the control inputs of the fifth and sixth regulated sources of bias-amplified field-effect transistors of the p-type conductivity, and the first, second, third and fourth regulated sources of voltage of the secondary voltage of the second converter the thirteenth and fourteenth amplifying field-effect transistors of n-type conductivity, the fifth, sixteenth, seventeenth and eighteenth amplifying field-effect transistors p-type conductivity and fifth, sixth, seventh and eighth regulated voltage sources pairing, in the third voltage converter in the mains entered the nineteenth and twentieth amplifying field-effect transistors of p-type conductivity, twenty-first, twenty-second, 0 twenty-third and twenty-fourth amplifying field-effect transistors of n-type conductivity and the ninth, tenth, eleventh and twelfth regulated sources of voltage of 5th voltage, the drain of the eighth amplifying field-effect transistor is connected to the drains of the first, second and seventh amplifying field-effect transistors, gate of the first field amplifier nor are they connected to the bus of the reference voltage of the transistor connected to the first inlet, the outlets of the fifth and sixth amplifiers of the first regulated source body field-effect transistors are connected to the inputs of the first and second current-voltage converters, respectively, the outputs of which are connected to the control inputs of the first, third, second, and fourth regulated sources of bias voltage, respectively, and the drain of the first and second amplifying field-effect transistors are interconnected and through the first resistor the loads are connected to the first power bus, the drains of the third and fourth amplifying field-effect transistors are interconnected and through the second load resistor connect The first and second amplifying field-effect transistors are respectively the first and second multiplier output buses, characterized in that, in order to broaden the dynamic range, improve accuracy and reduce power consumption, the seventh is introduced into the first voltage converter. and the eighth n-type field-effect transistors; the ninth, tenth, eleventh and twelfth five 0 five 0 five the voltage of the voltage, the second output of which is connected to the gate of the seventh amplifying field-effect transistor, the source of which is connected to the sources of the first, ninth and eleventh amplifying field-effect transistors, the gate of the eleventh amplification field-effect transistor is connected to the first output of the third adjustable voltage source of conjugation, the second output which is connected to the second output of the first adjustable source of bias voltage and the gate of the ninth amplifying field effect transistor n the second power bus, the drains of the tenth, eleventh and twelfth amplifying field-effect transistors, the gate of the twelfth amplifying transistor is connected to the first output of the fourth, adjustable conjugate voltage source, the second output of which is connected to the second output of the second adjustable source of bias voltage and the gate ten addition of a field-effect transistor, the source of which is connected to the sources of the second, eighth and twelfth field effect transistors, the gate of the eighth amplifying field-effect transistor is connected to the second output of the second regulated voltage source, the first terminal of which is connected to the gate of the second amplifying field-effect transistor, the drain of which is connected to the drain of the seventh amplifying field-effect transistor, and the control inputs of the first, second and second The third and fourth regulated sources of voltage are connected to the output of the first and second converters, respectively, current - voltage, drain four The tenth amplifying field-effect transistor is connected to the drain of the third field-effect transistor, the gate of which is connected to the first output of the fifth adjustable voltage source, the second end of which is connected to the gate of the thirteenth amplifying field-effect transistor, the source of which is connected to the sources of the third, fifth, and seventeenth field-effect amplifiers. transistors, the gate of the seventeenth amplifying field-effect transistor is connected to the first output of the seventh adjustable voltage source, the second The output of which is connected to the second output of the third adjustable bias voltage source and the gate of the fifteenth amplifying field-effect transistor, the drain of which is connected to the second power bus, the drain of the sixteenth, seventeenth and eighteenth amplifying field-effect transistors, the gate of the eighteenth amplifying field-effect transistor is connected to the first output eighth adjustable transistor voltage source, the second output of which is connected to the second output of the fourth adjustable voltage source bias and the gate of the sixteenth amplifying field-effect transistor, the source of which is connected to the sources of the fourth, fourteen and eighteenth amplifying field-effect transistors, the gate of the fourteenth amplifying field-effect transistor, is connected to the second output of the sixth adjustable voltage source, the first output of which is connected to the gate of the fourth amplifying field-effect transistor, the shade is connected to the fourth output of the sixth adjustable voltage source, the first terminal of which is connected to the gate of the fourth amplifying field-effect transistor, the shade is connected to the fourth output voltage of the sixth adjustable source of interfacing voltage, the first output of which is connected to the gate of the fourth amplifying field-effect transistor; which is connected to with. gokom trinadtsa 0 five Q g In addition, the control inputs of the fifth, seventh and sixth, eighth regulated voltage sources are connected respectively to the output of the first and second current-voltage converters, the drain of the twentieth amplifying field-effect transistor is connected to the drain of the fifth amplifying field-effect transistor, the gate of which connected to the first output of the ninth adjustable voltage source of conjugation, the second output of which is connected to the gate of the nineteenth amplifying field-effect transistor a, the source of which is connected to the sources of the fifth, twenty-first and twenty-third amplifying field-effect transistors, the gate of the twenty-third amplifying field-effect transistor is connected to the first output of the eleventh controlled voltage source, the second output of which is connected to the second output of the fifth adjustable voltage source the bias and the gate of the twenty-first amplifying field-effect transistor, the drain of which is connected to the first power bus and to the drains of the twenty-second, twenty-third and twenty The fourth amplifying field-effect transistors, the gate of the twenty-fourth amplifying field-effect transistor is connected to the first output of the twelfth adjustable voltage source, the second terminal of which is connected to the second output of the sixth adjustable voltage source of the biasing transistor, the source of which is connected to the sources the sixth, twentieth and twenty-fourth force field-effect transistors, the gate of the twentieth amplifying field. the transistor is connected to the second output of the tenth adjustable voltage source, the first output of which is connected to the gate of the sixth amplifying field-effect transistor, whose drain is connected to the drain of the nineteenth amplifying field-effect transistor, control inputs of the ninth, tenth, eleventh and twelfth adjustable sources of voltage mates are connected to the bus voltage reference. 0 five 0 0 five 2. The multiplier according to claim 1, is also distinguished by the fact that each adjustable source of bias voltage contains a twenty-fifth amplifying field effect transistor, twenty-sixth amplifying field effect transistor p -that conductivity and a first adjustable source of bias current, and chat the twenty-fifth amplifying field-effect transistor is the first output of the adjustable bias voltage source, the drain of the twenty-fifth amplifying field-effect transistor is connected to the first power line, and the source is connected to the source The twenty-sixth amplifying field effect transistor, the gate and drain of which is connected to the first output of the first controlled bias current source and is the second output of the controlled bias voltage source, the second output of the first adjustable current source is connected to the second power supply bus, and its control input is input control of an adjustable bias voltage source. 3. The multiplier of claim 1, characterized in that the fifth and sixth adjustable bias voltage sources each comprise a twenty-seventh amplifying field effect transistor of p-type conductivity and a twenty-eighth amplifying field effect transistor of n-type conductivity and a second adjustable bias current source, and the gate of the twenty-seventh amplifying field effect transistor is the first output of the fifth and sixth adjustable sources of bias voltage, the drain of the twenty-seventh amplifying field effect transistor is connected to the second The power supply bus, and its source is connected to the source of the twenty-eighth amplifying field effect transistor, the drain and gate of which is connected to the first output of the second controlled bias current source and is the second output of the fifth and sixth adjustable bias voltage sources, the second output of the second adjustable current source the bias is connected to the first power bus, and its control input is the control input of the fifth and sixth regulated sources of bias voltage. five 0 five 4, the multiplier of claim 1 0 five 0 five 0 five about those h and y u and s. By increasing the accuracy over a wide range of temperatures, the first, second, fifth, sixth, eleventh, and twelfth adjustable sources of interface voltage each contain twenty-ninth and thirtyth amplifying n-type field effect transistors, thirty-first and thirty-second p-type field-effect field-effect transistors and the first controlled mating current source, the gate of the twenty-ninth amplifying field-effect transistor being the first terminal of the first, second, fifth and sixth ones of the second voltage sources and the second output of the eleventh and twelve variable voltage sources, the drain of the twenty-ninth amplifying field-effect transistor is connected to the drain and gate of the thirty-first amplifying field-effect transistor and the gate of the thirty-second amplification field-effect transistor, the drain of which is connected the gate and drain of the thirtieth amplifying field effect transistor and is the second output of the first, second, fifth and sixth regulated sources of voltage mating and the first terminals of the eleventh and twelfth regulated voltage sources, the sources of twenty-ninth and thirtieth amplifying field-effect transistors are connected to the first terminal of the first controlled current source of coupling, the second terminal of which is connected to the second power bus, and the control input is the control input of the first , the second, fifth, sixth, eleventh and twelfth regulated voltage sources, and the sources of the thirty-first and thirty-second amplifying field-effect transistors in connected to the first power rail. 5. The multiplier according to claim 1, about tl and the fact that, in order to improve accuracy in a wide range of temperatures, the third, fourth, and from the seventh to the tenth controlled sources of conjugation voltage, contain every thirty third and thirty fourth field amplifiers, conduction transistors, thirty-fifth and thirty-sixth n-type field-effect field-effect transistors and a second regulated mating current source, with the gate of the thirty-third amplifying field-effect transistor being the second output of the third, fourth, seventh and eighth adjustable voltage sources and the first output the ninth and tenth regulated voltage sources, the drain of the thirty-third amplifying field-effect transistor is connected to the drain and the gate of the thirty-fifth of the amplifying field-effect transistor The thirty-sixth amplifier field-effect transistor, the drain of which is connected to the thirty-fourth amplification field effect transistor and the gate, is the first output of the third, fourth, seventh, and eighth controlled voltage sources and the second output of the ninth and ten adjustable the voltage sources, the sources of the thirty-third and thirty-fourth amplifying field-effect transistors are connected to the first output of the second regulated current source mating, Its output terminal is connected to the first power supply bus, and the control input is the control input of the third, fourth, and seventh to tenth regulated power sources, and the sources of the thirty-fifth and thirty-sixth amplifying field effect transistors are connected to the second power supply bus. . oezzh JAVN J Fia 2 Fa y 0 50  AND. # 76 Hf 51 FTSGZ Fi.g.ch Fi.g.e